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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 | /**************************************************************************** Copyright Echo Digital Audio Corporation (c) 1998 - 2004 All rights reserved www.echoaudio.com This file is part of Echo Digital Audio's generic driver library. Echo Digital Audio's generic driver library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ************************************************************************* Translation from C++ and adaptation for use in ALSA-Driver were made by Giuliano Pochini <pochini@shiny.it> ****************************************************************************/ static int write_control_reg(struct echoaudio *chip, u32 value, char force); static int set_input_clock(struct echoaudio *chip, u16 clock); static int set_professional_spdif(struct echoaudio *chip, char prof); static int set_digital_mode(struct echoaudio *chip, u8 mode); static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic); static int check_asic_status(struct echoaudio *chip); static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id) { int err; if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA)) return -ENODEV; err = init_dsp_comm_page(chip); if (err) { dev_err(chip->card->dev, "init_hw - could not initialize DSP comm page\n"); return err; } chip->device_id = device_id; chip->subdevice_id = subdevice_id; chip->bad_board = true; chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF | ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT; chip->digital_modes = ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA | ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL | ECHOCAPS_HAS_DIGITAL_MODE_ADAT; /* Mona comes in both '301 and '361 flavors */ if (chip->device_id == DEVICE_ID_56361) chip->dsp_code_to_load = FW_MONA_361_DSP; else chip->dsp_code_to_load = FW_MONA_301_DSP; err = load_firmware(chip); if (err < 0) return err; chip->bad_board = false; return err; } static int set_mixer_defaults(struct echoaudio *chip) { chip->digital_mode = DIGITAL_MODE_SPDIF_RCA; chip->professional_spdif = false; chip->digital_in_automute = true; return init_line_levels(chip); } static u32 detect_input_clocks(const struct echoaudio *chip) { u32 clocks_from_dsp, clock_bits; /* Map the DSP clock detect bits to the generic driver clock detect bits */ clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); clock_bits = ECHO_CLOCK_BIT_INTERNAL; if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF) clock_bits |= ECHO_CLOCK_BIT_SPDIF; if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT) clock_bits |= ECHO_CLOCK_BIT_ADAT; if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD) clock_bits |= ECHO_CLOCK_BIT_WORD; return clock_bits; } /* Mona has an ASIC on the PCI card and another ASIC in the external box; both need to be loaded. */ static int load_asic(struct echoaudio *chip) { u32 control_reg; int err; short asic; if (chip->asic_loaded) return 0; mdelay(10); if (chip->device_id == DEVICE_ID_56361) asic = FW_MONA_361_1_ASIC48; else asic = FW_MONA_301_1_ASIC48; err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic); if (err < 0) return err; chip->asic_code = asic; mdelay(10); /* Do the external one */ err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC, FW_MONA_2_ASIC); if (err < 0) return err; mdelay(10); err = check_asic_status(chip); /* Set up the control register if the load succeeded - 48 kHz, internal clock, S/PDIF RCA mode */ if (!err) { control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; err = write_control_reg(chip, control_reg, true); } return err; } /* Depending on what digital mode you want, Mona needs different ASICs loaded. This function checks the ASIC needed for the new mode and sees if it matches the one already loaded. */ static int switch_asic(struct echoaudio *chip, char double_speed) { int err; short asic; /* Check the clock detect bits to see if this is a single-speed clock or a double-speed clock; load a new ASIC if necessary. */ if (chip->device_id == DEVICE_ID_56361) { if (double_speed) asic = FW_MONA_361_1_ASIC96; else asic = FW_MONA_361_1_ASIC48; } else { if (double_speed) asic = FW_MONA_301_1_ASIC96; else asic = FW_MONA_301_1_ASIC48; } if (asic != chip->asic_code) { /* Load the desired ASIC */ err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic); if (err < 0) return err; chip->asic_code = asic; } return 0; } static int set_sample_rate(struct echoaudio *chip, u32 rate) { u32 control_reg, clock; short asic; char force_write; /* Only set the clock for internal mode. */ if (chip->input_clock != ECHO_CLOCK_INTERNAL) { dev_dbg(chip->card->dev, "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); /* Save the rate anyhow */ chip->comm_page->sample_rate = cpu_to_le32(rate); chip->sample_rate = rate; return 0; } /* Now, check to see if the required ASIC is loaded */ if (rate >= 88200) { if (chip->digital_mode == DIGITAL_MODE_ADAT) return -EINVAL; if (chip->device_id == DEVICE_ID_56361) asic = FW_MONA_361_1_ASIC96; else asic = FW_MONA_301_1_ASIC96; } else { if (chip->device_id == DEVICE_ID_56361) asic = FW_MONA_361_1_ASIC48; else asic = FW_MONA_301_1_ASIC48; } force_write = 0; if (asic != chip->asic_code) { int err; /* Load the desired ASIC (load_asic_generic() can sleep) */ spin_unlock_irq(&chip->lock); err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic); spin_lock_irq(&chip->lock); if (err < 0) return err; chip->asic_code = asic; force_write = 1; } /* Compute the new control register value */ clock = 0; control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg &= GML_CLOCK_CLEAR_MASK; control_reg &= GML_SPDIF_RATE_CLEAR_MASK; switch (rate) { case 96000: clock = GML_96KHZ; break; case 88200: clock = GML_88KHZ; break; case 48000: clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; break; case 44100: clock = GML_44KHZ; /* Professional mode */ if (control_reg & GML_SPDIF_PRO_MODE) clock |= GML_SPDIF_SAMPLE_RATE0; break; case 32000: clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | GML_SPDIF_SAMPLE_RATE1; break; case 22050: clock = GML_22KHZ; break; case 16000: clock = GML_16KHZ; break; case 11025: clock = GML_11KHZ; break; case 8000: clock = GML_8KHZ; break; default: dev_err(chip->card->dev, "set_sample_rate: %d invalid!\n", rate); return -EINVAL; } control_reg |= clock; chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ chip->sample_rate = rate; dev_dbg(chip->card->dev, "set_sample_rate: %d clock %d\n", rate, clock); return write_control_reg(chip, control_reg, force_write); } static int set_input_clock(struct echoaudio *chip, u16 clock) { u32 control_reg, clocks_from_dsp; int err; /* Mask off the clock select bits */ control_reg = le32_to_cpu(chip->comm_page->control_register) & GML_CLOCK_CLEAR_MASK; clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); switch (clock) { case ECHO_CLOCK_INTERNAL: chip->input_clock = ECHO_CLOCK_INTERNAL; return set_sample_rate(chip, chip->sample_rate); case ECHO_CLOCK_SPDIF: if (chip->digital_mode == DIGITAL_MODE_ADAT) return -EAGAIN; spin_unlock_irq(&chip->lock); err = switch_asic(chip, clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96); spin_lock_irq(&chip->lock); if (err < 0) return err; control_reg |= GML_SPDIF_CLOCK; if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96) control_reg |= GML_DOUBLE_SPEED_MODE; else control_reg &= ~GML_DOUBLE_SPEED_MODE; break; case ECHO_CLOCK_WORD: spin_unlock_irq(&chip->lock); err = switch_asic(chip, clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96); spin_lock_irq(&chip->lock); if (err < 0) return err; control_reg |= GML_WORD_CLOCK; if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96) control_reg |= GML_DOUBLE_SPEED_MODE; else control_reg &= ~GML_DOUBLE_SPEED_MODE; break; case ECHO_CLOCK_ADAT: dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n"); if (chip->digital_mode != DIGITAL_MODE_ADAT) return -EAGAIN; control_reg |= GML_ADAT_CLOCK; control_reg &= ~GML_DOUBLE_SPEED_MODE; break; default: dev_err(chip->card->dev, "Input clock 0x%x not supported for Mona\n", clock); return -EINVAL; } chip->input_clock = clock; return write_control_reg(chip, control_reg, true); } static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) { u32 control_reg; int err, incompatible_clock; /* Set clock to "internal" if it's not compatible with the new mode */ incompatible_clock = false; switch (mode) { case DIGITAL_MODE_SPDIF_OPTICAL: case DIGITAL_MODE_SPDIF_RCA: if (chip->input_clock == ECHO_CLOCK_ADAT) incompatible_clock = true; break; case DIGITAL_MODE_ADAT: if (chip->input_clock == ECHO_CLOCK_SPDIF) incompatible_clock = true; break; default: dev_err(chip->card->dev, "Digital mode not supported: %d\n", mode); return -EINVAL; } spin_lock_irq(&chip->lock); if (incompatible_clock) { /* Switch to 48KHz, internal */ chip->sample_rate = 48000; set_input_clock(chip, ECHO_CLOCK_INTERNAL); } /* Clear the current digital mode */ control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg &= GML_DIGITAL_MODE_CLEAR_MASK; /* Tweak the control reg */ switch (mode) { case DIGITAL_MODE_SPDIF_OPTICAL: control_reg |= GML_SPDIF_OPTICAL_MODE; break; case DIGITAL_MODE_SPDIF_RCA: /* GML_SPDIF_OPTICAL_MODE bit cleared */ break; case DIGITAL_MODE_ADAT: /* If the current ASIC is the 96KHz ASIC, switch the ASIC and set to 48 KHz */ if (chip->asic_code == FW_MONA_361_1_ASIC96 || chip->asic_code == FW_MONA_301_1_ASIC96) { set_sample_rate(chip, 48000); } control_reg |= GML_ADAT_MODE; control_reg &= ~GML_DOUBLE_SPEED_MODE; break; } err = write_control_reg(chip, control_reg, false); spin_unlock_irq(&chip->lock); if (err < 0) return err; chip->digital_mode = mode; dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode); return incompatible_clock; } |