Linux Audio

Check our new training course

Embedded Linux Audio

Check our new training course
with Creative Commons CC-BY-SA
lecture materials

Bootlin logo

Elixir Cross Referencer

Loading...
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2021 Alibaba Group Holding Limited.
 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
 */

#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "thead,th1520";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <3000000>;

		c910_0: cpu@0 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			reg = <0>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_1: cpu@1 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			reg = <1>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_2: cpu@2 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			reg = <2>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_3: cpu@3 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			reg = <3>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		l2_cache: l2-cache {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <1048576>;
			cache-sets = <1024>;
			cache-unified;
		};
	};

	osc: oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc_24m";
		#clock-cells = <0>;
	};

	osc_32k: 32k-oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc_32k";
		#clock-cells = <0>;
	};

	apb_clk: apb-clk-clock {
		compatible = "fixed-clock";
		clock-output-names = "apb_clk";
		#clock-cells = <0>;
	};

	uart_sclk: uart-sclk-clock {
		compatible = "fixed-clock";
		clock-output-names = "uart_sclk";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		plic: interrupt-controller@ffd8000000 {
			compatible = "thead,th1520-plic", "thead,c900-plic";
			reg = <0xff 0xd8000000 0x0 0x01000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
					      <&cpu1_intc 11>, <&cpu1_intc 9>,
					      <&cpu2_intc 11>, <&cpu2_intc 9>,
					      <&cpu3_intc 11>, <&cpu3_intc 9>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			riscv,ndev = <240>;
		};

		clint: timer@ffdc000000 {
			compatible = "thead,th1520-clint", "thead,c900-clint";
			reg = <0xff 0xdc000000 0x0 0x00010000>;
			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
					      <&cpu1_intc 3>, <&cpu1_intc 7>,
					      <&cpu2_intc 3>, <&cpu2_intc 7>,
					      <&cpu3_intc 3>, <&cpu3_intc 7>;
		};

		uart0: serial@ffe7014000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7014000 0x0 0x100>;
			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart1: serial@ffe7f00000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7f00000 0x0 0x100>;
			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart3: serial@ffe7f04000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7f04000 0x0 0x100>;
			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		gpio2: gpio@ffe7f34000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xe7f34000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio3: gpio@ffe7f38000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xe7f38000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portd: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio0: gpio@ffec005000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xec005000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@ffec006000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xec006000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		uart2: serial@ffec010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xec010000 0x0 0x4000>;
			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		dmac0: dma-controller@ffefc00000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0xff 0xefc00000 0x0 0x1000>;
			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb_clk>, <&apb_clk>;
			clock-names = "core-clk", "cfgr-clk";
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,block-size = <65536 65536 65536 65536>;
			snps,priority = <0 1 2 3>;
			snps,dma-masters = <1>;
			snps,data-width = <4>;
			snps,axi-max-burst-len = <16>;
			status = "disabled";
		};

		timer0: timer@ffefc32000 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32000 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer1: timer@ffefc32014 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32014 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer2: timer@ffefc32028 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32028 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer3: timer@ffefc3203c {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc3203c 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart4: serial@fff7f08000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xf7f08000 0x0 0x4000>;
			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart5: serial@fff7f0c000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xf7f0c000 0x0 0x4000>;
			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_sclk>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		timer4: timer@ffffc33000 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33000 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer5: timer@ffffc33014 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33014 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer6: timer@ffffc33028 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33028 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer7: timer@ffffc3303c {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc3303c 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ao_gpio0: gpio@fffff41000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xfff41000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porte: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		ao_gpio1: gpio@fffff52000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xfff52000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portf: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};