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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 | // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014, 2015 Intel Corporation * * Authors: * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> * * Maintained by: <tpmdd-devel@lists.sourceforge.net> * * This file contains TPM2 protocol implementations of the commands * used by the kernel internally. */ #include "tpm.h" #include <crypto/hash_info.h> static struct tpm2_hash tpm2_hash_map[] = { {HASH_ALGO_SHA1, TPM_ALG_SHA1}, {HASH_ALGO_SHA256, TPM_ALG_SHA256}, {HASH_ALGO_SHA384, TPM_ALG_SHA384}, {HASH_ALGO_SHA512, TPM_ALG_SHA512}, {HASH_ALGO_SM3_256, TPM_ALG_SM3_256}, }; int tpm2_get_timeouts(struct tpm_chip *chip) { /* Fixed timeouts for TPM2 */ chip->timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A); chip->timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B); chip->timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C); chip->timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D); /* PTP spec timeouts */ chip->duration[TPM_SHORT] = msecs_to_jiffies(TPM2_DURATION_SHORT); chip->duration[TPM_MEDIUM] = msecs_to_jiffies(TPM2_DURATION_MEDIUM); chip->duration[TPM_LONG] = msecs_to_jiffies(TPM2_DURATION_LONG); /* Key creation commands long timeouts */ chip->duration[TPM_LONG_LONG] = msecs_to_jiffies(TPM2_DURATION_LONG_LONG); chip->flags |= TPM_CHIP_FLAG_HAVE_TIMEOUTS; return 0; } /** * tpm2_ordinal_duration_index() - returns an index to the chip duration table * @ordinal: TPM command ordinal. * * The function returns an index to the chip duration table * (enum tpm_duration), that describes the maximum amount of * time the chip could take to return the result for a particular ordinal. * * The values of the MEDIUM, and LONG durations are taken * from the PC Client Profile (PTP) specification (750, 2000 msec) * * LONG_LONG is for commands that generates keys which empirically takes * a longer time on some systems. * * Return: * * TPM_MEDIUM * * TPM_LONG * * TPM_LONG_LONG * * TPM_UNDEFINED */ static u8 tpm2_ordinal_duration_index(u32 ordinal) { switch (ordinal) { /* Startup */ case TPM2_CC_STARTUP: /* 144 */ return TPM_MEDIUM; case TPM2_CC_SELF_TEST: /* 143 */ return TPM_LONG; case TPM2_CC_GET_RANDOM: /* 17B */ return TPM_LONG; case TPM2_CC_SEQUENCE_UPDATE: /* 15C */ return TPM_MEDIUM; case TPM2_CC_SEQUENCE_COMPLETE: /* 13E */ return TPM_MEDIUM; case TPM2_CC_EVENT_SEQUENCE_COMPLETE: /* 185 */ return TPM_MEDIUM; case TPM2_CC_HASH_SEQUENCE_START: /* 186 */ return TPM_MEDIUM; case TPM2_CC_VERIFY_SIGNATURE: /* 177 */ return TPM_LONG_LONG; case TPM2_CC_PCR_EXTEND: /* 182 */ return TPM_MEDIUM; case TPM2_CC_HIERARCHY_CONTROL: /* 121 */ return TPM_LONG; case TPM2_CC_HIERARCHY_CHANGE_AUTH: /* 129 */ return TPM_LONG; case TPM2_CC_GET_CAPABILITY: /* 17A */ return TPM_MEDIUM; case TPM2_CC_NV_READ: /* 14E */ return TPM_LONG; case TPM2_CC_CREATE_PRIMARY: /* 131 */ return TPM_LONG_LONG; case TPM2_CC_CREATE: /* 153 */ return TPM_LONG_LONG; case TPM2_CC_CREATE_LOADED: /* 191 */ return TPM_LONG_LONG; default: return TPM_UNDEFINED; } } /** * tpm2_calc_ordinal_duration() - calculate the maximum command duration * @chip: TPM chip to use. * @ordinal: TPM command ordinal. * * The function returns the maximum amount of time the chip could take * to return the result for a particular ordinal in jiffies. * * Return: A maximal duration time for an ordinal in jiffies. */ unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal) { unsigned int index; index = tpm2_ordinal_duration_index(ordinal); if (index != TPM_UNDEFINED) return chip->duration[index]; else return msecs_to_jiffies(TPM2_DURATION_DEFAULT); } struct tpm2_pcr_read_out { __be32 update_cnt; __be32 pcr_selects_cnt; __be16 hash_alg; u8 pcr_select_size; u8 pcr_select[TPM2_PCR_SELECT_MIN]; __be32 digests_cnt; __be16 digest_size; u8 digest[]; } __packed; /** * tpm2_pcr_read() - read a PCR value * @chip: TPM chip to use. * @pcr_idx: index of the PCR to read. * @digest: PCR bank and buffer current PCR value is written to. * @digest_size_ptr: pointer to variable that stores the digest size. * * Return: Same as with tpm_transmit_cmd. */ int tpm2_pcr_read(struct tpm_chip *chip, u32 pcr_idx, struct tpm_digest *digest, u16 *digest_size_ptr) { int i; int rc; struct tpm_buf buf; struct tpm2_pcr_read_out *out; u8 pcr_select[TPM2_PCR_SELECT_MIN] = {0}; u16 digest_size; u16 expected_digest_size = 0; if (pcr_idx >= TPM2_PLATFORM_PCR) return -EINVAL; if (!digest_size_ptr) { for (i = 0; i < chip->nr_allocated_banks && chip->allocated_banks[i].alg_id != digest->alg_id; i++) ; if (i == chip->nr_allocated_banks) return -EINVAL; expected_digest_size = chip->allocated_banks[i].digest_size; } rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_PCR_READ); if (rc) return rc; pcr_select[pcr_idx >> 3] = 1 << (pcr_idx & 0x7); tpm_buf_append_u32(&buf, 1); tpm_buf_append_u16(&buf, digest->alg_id); tpm_buf_append_u8(&buf, TPM2_PCR_SELECT_MIN); tpm_buf_append(&buf, (const unsigned char *)pcr_select, sizeof(pcr_select)); rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to read a pcr value"); if (rc) goto out; out = (struct tpm2_pcr_read_out *)&buf.data[TPM_HEADER_SIZE]; digest_size = be16_to_cpu(out->digest_size); if (digest_size > sizeof(digest->digest) || (!digest_size_ptr && digest_size != expected_digest_size)) { rc = -EINVAL; goto out; } if (digest_size_ptr) *digest_size_ptr = digest_size; memcpy(digest->digest, out->digest, digest_size); out: tpm_buf_destroy(&buf); return rc; } struct tpm2_null_auth_area { __be32 handle; __be16 nonce_size; u8 attributes; __be16 auth_size; } __packed; /** * tpm2_pcr_extend() - extend a PCR value * * @chip: TPM chip to use. * @pcr_idx: index of the PCR. * @digests: list of pcr banks and corresponding digest values to extend. * * Return: Same as with tpm_transmit_cmd. */ int tpm2_pcr_extend(struct tpm_chip *chip, u32 pcr_idx, struct tpm_digest *digests) { struct tpm_buf buf; struct tpm2_null_auth_area auth_area; int rc; int i; rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_PCR_EXTEND); if (rc) return rc; tpm_buf_append_u32(&buf, pcr_idx); auth_area.handle = cpu_to_be32(TPM2_RS_PW); auth_area.nonce_size = 0; auth_area.attributes = 0; auth_area.auth_size = 0; tpm_buf_append_u32(&buf, sizeof(struct tpm2_null_auth_area)); tpm_buf_append(&buf, (const unsigned char *)&auth_area, sizeof(auth_area)); tpm_buf_append_u32(&buf, chip->nr_allocated_banks); for (i = 0; i < chip->nr_allocated_banks; i++) { tpm_buf_append_u16(&buf, digests[i].alg_id); tpm_buf_append(&buf, (const unsigned char *)&digests[i].digest, chip->allocated_banks[i].digest_size); } rc = tpm_transmit_cmd(chip, &buf, 0, "attempting extend a PCR value"); tpm_buf_destroy(&buf); return rc; } struct tpm2_get_random_out { __be16 size; u8 buffer[TPM_MAX_RNG_DATA]; } __packed; /** * tpm2_get_random() - get random bytes from the TPM RNG * * @chip: a &tpm_chip instance * @dest: destination buffer * @max: the max number of random bytes to pull * * Return: * size of the buffer on success, * -errno otherwise (positive TPM return codes are masked to -EIO) */ int tpm2_get_random(struct tpm_chip *chip, u8 *dest, size_t max) { struct tpm2_get_random_out *out; struct tpm_buf buf; u32 recd; u32 num_bytes = max; int err; int total = 0; int retries = 5; u8 *dest_ptr = dest; if (!num_bytes || max > TPM_MAX_RNG_DATA) return -EINVAL; err = tpm_buf_init(&buf, 0, 0); if (err) return err; do { tpm_buf_reset(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_RANDOM); tpm_buf_append_u16(&buf, num_bytes); err = tpm_transmit_cmd(chip, &buf, offsetof(struct tpm2_get_random_out, buffer), "attempting get random"); if (err) { if (err > 0) err = -EIO; goto out; } out = (struct tpm2_get_random_out *) &buf.data[TPM_HEADER_SIZE]; recd = min_t(u32, be16_to_cpu(out->size), num_bytes); if (tpm_buf_length(&buf) < TPM_HEADER_SIZE + offsetof(struct tpm2_get_random_out, buffer) + recd) { err = -EFAULT; goto out; } memcpy(dest_ptr, out->buffer, recd); dest_ptr += recd; total += recd; num_bytes -= recd; } while (retries-- && total < max); tpm_buf_destroy(&buf); return total ? total : -EIO; out: tpm_buf_destroy(&buf); return err; } /** * tpm2_flush_context() - execute a TPM2_FlushContext command * @chip: TPM chip to use * @handle: context handle */ void tpm2_flush_context(struct tpm_chip *chip, u32 handle) { struct tpm_buf buf; int rc; rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_FLUSH_CONTEXT); if (rc) { dev_warn(&chip->dev, "0x%08x was not flushed, out of memory\n", handle); return; } tpm_buf_append_u32(&buf, handle); tpm_transmit_cmd(chip, &buf, 0, "flushing context"); tpm_buf_destroy(&buf); } EXPORT_SYMBOL_GPL(tpm2_flush_context); struct tpm2_get_cap_out { u8 more_data; __be32 subcap_id; __be32 property_cnt; __be32 property_id; __be32 value; } __packed; /** * tpm2_get_tpm_pt() - get value of a TPM_CAP_TPM_PROPERTIES type property * @chip: a &tpm_chip instance * @property_id: property ID. * @value: output variable. * @desc: passed to tpm_transmit_cmd() * * Return: * 0 on success, * -errno or a TPM return code otherwise */ ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id, u32 *value, const char *desc) { struct tpm2_get_cap_out *out; struct tpm_buf buf; int rc; rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY); if (rc) return rc; tpm_buf_append_u32(&buf, TPM2_CAP_TPM_PROPERTIES); tpm_buf_append_u32(&buf, property_id); tpm_buf_append_u32(&buf, 1); rc = tpm_transmit_cmd(chip, &buf, 0, NULL); if (!rc) { out = (struct tpm2_get_cap_out *) &buf.data[TPM_HEADER_SIZE]; /* * To prevent failing boot up of some systems, Infineon TPM2.0 * returns SUCCESS on TPM2_Startup in field upgrade mode. Also * the TPM2_Getcapability command returns a zero length list * in field upgrade mode. */ if (be32_to_cpu(out->property_cnt) > 0) *value = be32_to_cpu(out->value); else rc = -ENODATA; } tpm_buf_destroy(&buf); return rc; } EXPORT_SYMBOL_GPL(tpm2_get_tpm_pt); /** * tpm2_shutdown() - send a TPM shutdown command * * Sends a TPM shutdown command. The shutdown command is used in call * sites where the system is going down. If it fails, there is not much * that can be done except print an error message. * * @chip: a &tpm_chip instance * @shutdown_type: TPM_SU_CLEAR or TPM_SU_STATE. */ void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type) { struct tpm_buf buf; int rc; rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_SHUTDOWN); if (rc) return; tpm_buf_append_u16(&buf, shutdown_type); tpm_transmit_cmd(chip, &buf, 0, "stopping the TPM"); tpm_buf_destroy(&buf); } /** * tpm2_do_selftest() - ensure that all self tests have passed * * @chip: TPM chip to use * * Return: Same as with tpm_transmit_cmd. * * The TPM can either run all self tests synchronously and then return * RC_SUCCESS once all tests were successful. Or it can choose to run the tests * asynchronously and return RC_TESTING immediately while the self tests still * execute in the background. This function handles both cases and waits until * all tests have completed. */ static int tpm2_do_selftest(struct tpm_chip *chip) { struct tpm_buf buf; int full; int rc; for (full = 0; full < 2; full++) { rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_SELF_TEST); if (rc) return rc; tpm_buf_append_u8(&buf, full); rc = tpm_transmit_cmd(chip, &buf, 0, "attempting the self test"); tpm_buf_destroy(&buf); if (rc == TPM2_RC_TESTING) rc = TPM2_RC_SUCCESS; if (rc == TPM2_RC_INITIALIZE || rc == TPM2_RC_SUCCESS) return rc; } return rc; } /** * tpm2_probe() - probe for the TPM 2.0 protocol * @chip: a &tpm_chip instance * * Send an idempotent TPM 2.0 command and see whether there is TPM2 chip in the * other end based on the response tag. The flag TPM_CHIP_FLAG_TPM2 is set by * this function if this is the case. * * Return: * 0 on success, * -errno otherwise */ int tpm2_probe(struct tpm_chip *chip) { struct tpm_header *out; struct tpm_buf buf; int rc; rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY); if (rc) return rc; tpm_buf_append_u32(&buf, TPM2_CAP_TPM_PROPERTIES); tpm_buf_append_u32(&buf, TPM_PT_TOTAL_COMMANDS); tpm_buf_append_u32(&buf, 1); rc = tpm_transmit_cmd(chip, &buf, 0, NULL); /* We ignore TPM return codes on purpose. */ if (rc >= 0) { out = (struct tpm_header *)buf.data; if (be16_to_cpu(out->tag) == TPM2_ST_NO_SESSIONS) chip->flags |= TPM_CHIP_FLAG_TPM2; } tpm_buf_destroy(&buf); return 0; } EXPORT_SYMBOL_GPL(tpm2_probe); static int tpm2_init_bank_info(struct tpm_chip *chip, u32 bank_index) { struct tpm_bank_info *bank = chip->allocated_banks + bank_index; struct tpm_digest digest = { .alg_id = bank->alg_id }; int i; /* * Avoid unnecessary PCR read operations to reduce overhead * and obtain identifiers of the crypto subsystem. */ for (i = 0; i < ARRAY_SIZE(tpm2_hash_map); i++) { enum hash_algo crypto_algo = tpm2_hash_map[i].crypto_id; if (bank->alg_id != tpm2_hash_map[i].tpm_id) continue; bank->digest_size = hash_digest_size[crypto_algo]; bank->crypto_id = crypto_algo; return 0; } bank->crypto_id = HASH_ALGO__LAST; return tpm2_pcr_read(chip, 0, &digest, &bank->digest_size); } struct tpm2_pcr_selection { __be16 hash_alg; u8 size_of_select; u8 pcr_select[3]; } __packed; ssize_t tpm2_get_pcr_allocation(struct tpm_chip *chip) { struct tpm2_pcr_selection pcr_selection; struct tpm_buf buf; void *marker; void *end; void *pcr_select_offset; u32 sizeof_pcr_selection; u32 nr_possible_banks; u32 nr_alloc_banks = 0; u16 hash_alg; u32 rsp_len; int rc; int i = 0; rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY); if (rc) return rc; tpm_buf_append_u32(&buf, TPM2_CAP_PCRS); tpm_buf_append_u32(&buf, 0); tpm_buf_append_u32(&buf, 1); rc = tpm_transmit_cmd(chip, &buf, 9, "get tpm pcr allocation"); if (rc) goto out; nr_possible_banks = be32_to_cpup( (__be32 *)&buf.data[TPM_HEADER_SIZE + 5]); chip->allocated_banks = kcalloc(nr_possible_banks, sizeof(*chip->allocated_banks), GFP_KERNEL); if (!chip->allocated_banks) { rc = -ENOMEM; goto out; } marker = &buf.data[TPM_HEADER_SIZE + 9]; rsp_len = be32_to_cpup((__be32 *)&buf.data[2]); end = &buf.data[rsp_len]; for (i = 0; i < nr_possible_banks; i++) { pcr_select_offset = marker + offsetof(struct tpm2_pcr_selection, size_of_select); if (pcr_select_offset >= end) { rc = -EFAULT; break; } memcpy(&pcr_selection, marker, sizeof(pcr_selection)); hash_alg = be16_to_cpu(pcr_selection.hash_alg); pcr_select_offset = memchr_inv(pcr_selection.pcr_select, 0, pcr_selection.size_of_select); if (pcr_select_offset) { chip->allocated_banks[nr_alloc_banks].alg_id = hash_alg; rc = tpm2_init_bank_info(chip, nr_alloc_banks); if (rc < 0) break; nr_alloc_banks++; } sizeof_pcr_selection = sizeof(pcr_selection.hash_alg) + sizeof(pcr_selection.size_of_select) + pcr_selection.size_of_select; marker = marker + sizeof_pcr_selection; } chip->nr_allocated_banks = nr_alloc_banks; out: tpm_buf_destroy(&buf); return rc; } int tpm2_get_cc_attrs_tbl(struct tpm_chip *chip) { struct tpm_buf buf; u32 nr_commands; __be32 *attrs; u32 cc; int i; int rc; rc = tpm2_get_tpm_pt(chip, TPM_PT_TOTAL_COMMANDS, &nr_commands, NULL); if (rc) goto out; if (nr_commands > 0xFFFFF) { rc = -EFAULT; goto out; } chip->cc_attrs_tbl = devm_kcalloc(&chip->dev, 4, nr_commands, GFP_KERNEL); if (!chip->cc_attrs_tbl) { rc = -ENOMEM; goto out; } rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY); if (rc) goto out; tpm_buf_append_u32(&buf, TPM2_CAP_COMMANDS); tpm_buf_append_u32(&buf, TPM2_CC_FIRST); tpm_buf_append_u32(&buf, nr_commands); rc = tpm_transmit_cmd(chip, &buf, 9 + 4 * nr_commands, NULL); if (rc) { tpm_buf_destroy(&buf); goto out; } if (nr_commands != be32_to_cpup((__be32 *)&buf.data[TPM_HEADER_SIZE + 5])) { rc = -EFAULT; tpm_buf_destroy(&buf); goto out; } chip->nr_commands = nr_commands; attrs = (__be32 *)&buf.data[TPM_HEADER_SIZE + 9]; for (i = 0; i < nr_commands; i++, attrs++) { chip->cc_attrs_tbl[i] = be32_to_cpup(attrs); cc = chip->cc_attrs_tbl[i] & 0xFFFF; if (cc == TPM2_CC_CONTEXT_SAVE || cc == TPM2_CC_FLUSH_CONTEXT) { chip->cc_attrs_tbl[i] &= ~(GENMASK(2, 0) << TPM2_CC_ATTR_CHANDLES); chip->cc_attrs_tbl[i] |= 1 << TPM2_CC_ATTR_CHANDLES; } } tpm_buf_destroy(&buf); out: if (rc > 0) rc = -ENODEV; return rc; } EXPORT_SYMBOL_GPL(tpm2_get_cc_attrs_tbl); /** * tpm2_startup - turn on the TPM * @chip: TPM chip to use * * Normally the firmware should start the TPM. This function is provided as a * workaround if this does not happen. A legal case for this could be for * example when a TPM emulator is used. * * Return: same as tpm_transmit_cmd() */ static int tpm2_startup(struct tpm_chip *chip) { struct tpm_buf buf; int rc; dev_info(&chip->dev, "starting up the TPM manually\n"); rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_STARTUP); if (rc < 0) return rc; tpm_buf_append_u16(&buf, TPM2_SU_CLEAR); rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to start the TPM"); tpm_buf_destroy(&buf); return rc; } /** * tpm2_auto_startup - Perform the standard automatic TPM initialization * sequence * @chip: TPM chip to use * * Returns 0 on success, < 0 in case of fatal error. */ int tpm2_auto_startup(struct tpm_chip *chip) { int rc; rc = tpm2_get_timeouts(chip); if (rc) goto out; rc = tpm2_do_selftest(chip); if (rc && rc != TPM2_RC_INITIALIZE) goto out; if (rc == TPM2_RC_INITIALIZE) { rc = tpm2_startup(chip); if (rc) goto out; rc = tpm2_do_selftest(chip); if (rc) goto out; } rc = tpm2_get_cc_attrs_tbl(chip); if (rc == TPM2_RC_FAILURE || (rc < 0 && rc != -ENOMEM)) { dev_info(&chip->dev, "TPM in field failure mode, requires firmware upgrade\n"); chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE; rc = 0; } out: /* * Infineon TPM in field upgrade mode will return no data for the number * of supported commands. */ if (rc == TPM2_RC_UPGRADE || rc == -ENODATA) { dev_info(&chip->dev, "TPM in field upgrade mode, requires firmware upgrade\n"); chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE; rc = 0; } if (rc > 0) rc = -ENODEV; return rc; } int tpm2_find_cc(struct tpm_chip *chip, u32 cc) { u32 cc_mask; int i; cc_mask = 1 << TPM2_CC_ATTR_VENDOR | GENMASK(15, 0); for (i = 0; i < chip->nr_commands; i++) if (cc == (chip->cc_attrs_tbl[i] & cc_mask)) return i; return -1; } |