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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2018-2020 NXP * Dong Aisheng <aisheng.dong@nxp.com> */ #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, <0x08000000 0x0 0x08000000 0x10000000>; lsio_mem_clk: clock-lsio-mem { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; clock-output-names = "lsio_mem_clk"; }; lsio_bus_clk: clock-lsio-bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "lsio_bus_clk"; }; lsio_pwm0: pwm@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d000000 0x10000>; clock-names = "ipg", "per"; clocks = <&pwm0_lpcg 4>, <&pwm0_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <2>; status = "disabled"; }; lsio_pwm1: pwm@5d010000 { compatible = "fsl,imx27-pwm"; reg = <0x5d010000 0x10000>; clock-names = "ipg", "per"; clocks = <&pwm1_lpcg 4>, <&pwm1_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <2>; status = "disabled"; }; lsio_pwm2: pwm@5d020000 { compatible = "fsl,imx27-pwm"; reg = <0x5d020000 0x10000>; clock-names = "ipg", "per"; clocks = <&pwm2_lpcg 4>, <&pwm2_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <2>; status = "disabled"; }; lsio_pwm3: pwm@5d030000 { compatible = "fsl,imx27-pwm"; reg = <0x5d030000 0x10000>; clock-names = "ipg", "per"; clocks = <&pwm3_lpcg 4>, <&pwm3_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <2>; status = "disabled"; }; lsio_gpio0: gpio@5d080000 { reg = <0x5d080000 0x10000>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_0>; }; lsio_gpio1: gpio@5d090000 { reg = <0x5d090000 0x10000>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_1>; }; lsio_gpio2: gpio@5d0a0000 { reg = <0x5d0a0000 0x10000>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_2>; }; lsio_gpio3: gpio@5d0b0000 { reg = <0x5d0b0000 0x10000>; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_3>; }; lsio_gpio4: gpio@5d0c0000 { reg = <0x5d0c0000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_4>; }; lsio_gpio5: gpio@5d0d0000 { reg = <0x5d0d0000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_5>; }; lsio_gpio6: gpio@5d0e0000 { reg = <0x5d0e0000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_6>; }; lsio_gpio7: gpio@5d0f0000 { reg = <0x5d0f0000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_7>; }; flexspi0: spi@5d120000 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,imx8qxp-fspi"; reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; clock-names = "fspi_en", "fspi"; power-domains = <&pd IMX_SC_R_FSPI_0>; status = "disabled"; }; lsio_mu0: mailbox@5d1b0000 { reg = <0x5d1b0000 0x10000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; status = "disabled"; }; lsio_mu1: mailbox@5d1c0000 { reg = <0x5d1c0000 0x10000>; interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; }; lsio_mu2: mailbox@5d1d0000 { reg = <0x5d1d0000 0x10000>; interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; status = "disabled"; }; lsio_mu3: mailbox@5d1e0000 { reg = <0x5d1e0000 0x10000>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; status = "disabled"; }; lsio_mu4: mailbox@5d1f0000 { reg = <0x5d1f0000 0x10000>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; status = "disabled"; }; lsio_mu5: mailbox@5d200000 { reg = <0x5d200000 0x10000>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_MU_5A>; status = "disabled"; }; lsio_mu6: mailbox@5d210000 { reg = <0x5d210000 0x10000>; interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_MU_6A>; status = "disabled"; }; lsio_mu13: mailbox@5d280000 { reg = <0x5d280000 0x10000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_MU_13A>; }; /* LPCG clocks */ pwm0_lpcg: clock-controller@5d400000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d400000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm0_lpcg_ipg_clk", "pwm0_lpcg_ipg_hf_clk", "pwm0_lpcg_ipg_s_clk", "pwm0_lpcg_ipg_slv_clk", "pwm0_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_0>; }; pwm1_lpcg: clock-controller@5d410000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d410000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm1_lpcg_ipg_clk", "pwm1_lpcg_ipg_hf_clk", "pwm1_lpcg_ipg_s_clk", "pwm1_lpcg_ipg_slv_clk", "pwm1_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_1>; }; pwm2_lpcg: clock-controller@5d420000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d420000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm2_lpcg_ipg_clk", "pwm2_lpcg_ipg_hf_clk", "pwm2_lpcg_ipg_s_clk", "pwm2_lpcg_ipg_slv_clk", "pwm2_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_2>; }; pwm3_lpcg: clock-controller@5d430000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d430000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm3_lpcg_ipg_clk", "pwm3_lpcg_ipg_hf_clk", "pwm3_lpcg_ipg_s_clk", "pwm3_lpcg_ipg_slv_clk", "pwm3_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_3>; }; pwm4_lpcg: clock-controller@5d440000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d440000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm4_lpcg_ipg_clk", "pwm4_lpcg_ipg_hf_clk", "pwm4_lpcg_ipg_s_clk", "pwm4_lpcg_ipg_slv_clk", "pwm4_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_4>; }; pwm5_lpcg: clock-controller@5d450000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d450000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm5_lpcg_ipg_clk", "pwm5_lpcg_ipg_hf_clk", "pwm5_lpcg_ipg_s_clk", "pwm5_lpcg_ipg_slv_clk", "pwm5_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_5>; }; pwm6_lpcg: clock-controller@5d460000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm6_lpcg_ipg_clk", "pwm6_lpcg_ipg_hf_clk", "pwm6_lpcg_ipg_s_clk", "pwm6_lpcg_ipg_slv_clk", "pwm6_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_6>; }; pwm7_lpcg: clock-controller@5d470000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d470000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; clock-output-names = "pwm7_lpcg_ipg_clk", "pwm7_lpcg_ipg_hf_clk", "pwm7_lpcg_ipg_s_clk", "pwm7_lpcg_ipg_slv_clk", "pwm7_lpcg_ipg_mstr_clk"; power-domains = <&pd IMX_SC_R_PWM_7>; }; }; |