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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 | /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2013 NVIDIA Corporation * Copyright (C) 2018 Cadence Design Systems Inc. */ #include <linux/errno.h> #include <linux/export.h> #include <linux/kernel.h> #include <linux/time64.h> #include <linux/phy/phy.h> #include <linux/phy/phy-mipi-dphy.h> /* * Minimum D-PHY timings based on MIPI D-PHY specification. Derived * from the valid ranges specified in Section 6.9, Table 14, Page 41 * of the D-PHY specification (v1.2). */ static int phy_mipi_dphy_calc_config(unsigned long pixel_clock, unsigned int bpp, unsigned int lanes, unsigned long long hs_clk_rate, struct phy_configure_opts_mipi_dphy *cfg) { unsigned long long ui; if (!cfg) return -EINVAL; if (!hs_clk_rate) { hs_clk_rate = pixel_clock * bpp; do_div(hs_clk_rate, lanes); } ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); do_div(ui, hs_clk_rate); cfg->clk_miss = 0; cfg->clk_post = 60000 + 52 * ui; cfg->clk_pre = 8; cfg->clk_prepare = 38000; cfg->clk_settle = 95000; cfg->clk_term_en = 0; cfg->clk_trail = 60000; cfg->clk_zero = 262000; cfg->d_term_en = 0; cfg->eot = 0; cfg->hs_exit = 100000; cfg->hs_prepare = 40000 + 4 * ui; cfg->hs_zero = 105000 + 6 * ui; cfg->hs_settle = 85000 + 6 * ui; cfg->hs_skip = 40000; /* * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) * contains this formula as: * * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) * * where n = 1 for forward-direction HS mode and n = 4 for reverse- * direction HS mode. There's only one setting and this function does * not parameterize on anything other that ui, so this code will * assumes that reverse-direction HS mode is supported and uses n = 4. */ cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); cfg->init = 100; cfg->lpx = 50000; cfg->ta_get = 5 * cfg->lpx; cfg->ta_go = 4 * cfg->lpx; cfg->ta_sure = cfg->lpx; cfg->wakeup = 1000; cfg->hs_clk_rate = hs_clk_rate; cfg->lanes = lanes; return 0; } int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, unsigned int bpp, unsigned int lanes, struct phy_configure_opts_mipi_dphy *cfg) { return phy_mipi_dphy_calc_config(pixel_clock, bpp, lanes, 0, cfg); } EXPORT_SYMBOL(phy_mipi_dphy_get_default_config); int phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate, unsigned int lanes, struct phy_configure_opts_mipi_dphy *cfg) { if (!hs_clk_rate) return -EINVAL; return phy_mipi_dphy_calc_config(0, 0, lanes, hs_clk_rate, cfg); } EXPORT_SYMBOL(phy_mipi_dphy_get_default_config_for_hsclk); /* * Validate D-PHY configuration according to MIPI D-PHY specification * (v1.2, Section Section 6.9 "Global Operation Timing Parameters"). */ int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg) { unsigned long long ui; if (!cfg) return -EINVAL; ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); do_div(ui, cfg->hs_clk_rate); if (cfg->clk_miss > 60000) return -EINVAL; if (cfg->clk_post < (60000 + 52 * ui)) return -EINVAL; if (cfg->clk_pre < 8) return -EINVAL; if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000) return -EINVAL; if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000) return -EINVAL; if (cfg->clk_term_en > 38000) return -EINVAL; if (cfg->clk_trail < 60000) return -EINVAL; if ((cfg->clk_prepare + cfg->clk_zero) < 300000) return -EINVAL; if (cfg->d_term_en > (35000 + 4 * ui)) return -EINVAL; if (cfg->eot > (105000 + 12 * ui)) return -EINVAL; if (cfg->hs_exit < 100000) return -EINVAL; if (cfg->hs_prepare < (40000 + 4 * ui) || cfg->hs_prepare > (85000 + 6 * ui)) return -EINVAL; if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui)) return -EINVAL; if ((cfg->hs_settle < (85000 + 6 * ui)) || (cfg->hs_settle > (145000 + 10 * ui))) return -EINVAL; if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui)) return -EINVAL; if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui)) return -EINVAL; if (cfg->init < 100) return -EINVAL; if (cfg->lpx < 50000) return -EINVAL; if (cfg->ta_get != (5 * cfg->lpx)) return -EINVAL; if (cfg->ta_go != (4 * cfg->lpx)) return -EINVAL; if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx)) return -EINVAL; if (cfg->wakeup < 1000) return -EINVAL; return 0; } EXPORT_SYMBOL(phy_mipi_dphy_config_validate); |