Linux Audio

Check our new training course

Embedded Linux Audio

Check our new training course
with Creative Commons CC-BY-SA
lecture materials

Bootlin logo

Elixir Cross Referencer

Loading...
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
[
    {
        "BriefDescription": "AMX retired arithmetic BF16 operations.",
        "EventCode": "0xce",
        "EventName": "AMX_OPS_RETIRED.BF16",
        "PublicDescription": "Number of AMX-based retired arithmetic bfloat16 (BF16) floating-point operations. Counts TDPBF16PS FP instructions. SW to use operation multiplier of 4",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "AMX retired arithmetic integer 8-bit operations.",
        "EventCode": "0xce",
        "EventName": "AMX_OPS_RETIRED.INT8",
        "PublicDescription": "Number of AMX-based retired arithmetic integer operations of 8-bit width source operands. Counts TDPB[SS,UU,US,SU]D instructions. SW should use operation multiplier of 8.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE",
        "CounterMask": "1",
        "Deprecated": "1",
        "EventCode": "0xb0",
        "EventName": "ARITH.DIVIDER_ACTIVE",
        "SampleAfterValue": "1000003",
        "UMask": "0x9"
    },
    {
        "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
        "CounterMask": "1",
        "EventCode": "0xb0",
        "EventName": "ARITH.DIV_ACTIVE",
        "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
        "SampleAfterValue": "1000003",
        "UMask": "0x9"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE",
        "CounterMask": "1",
        "Deprecated": "1",
        "EventCode": "0xb0",
        "EventName": "ARITH.FP_DIVIDER_ACTIVE",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event counts the cycles the integer divider is busy.",
        "CounterMask": "1",
        "EventCode": "0xb0",
        "EventName": "ARITH.IDIV_ACTIVE",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE",
        "CounterMask": "1",
        "Deprecated": "1",
        "EventCode": "0xb0",
        "EventName": "ARITH.INT_DIVIDER_ACTIVE",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.ANY",
        "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
        "SampleAfterValue": "100003",
        "UMask": "0x1b"
    },
    {
        "BriefDescription": "All branch instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "PEBS": "1",
        "PublicDescription": "Counts all branch instructions retired.",
        "SampleAfterValue": "400009"
    },
    {
        "BriefDescription": "Conditional branch instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.COND",
        "PEBS": "1",
        "PublicDescription": "Counts conditional branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x11"
    },
    {
        "BriefDescription": "Not taken branch instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.COND_NTAKEN",
        "PEBS": "1",
        "PublicDescription": "Counts not taken branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Taken conditional branch instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.COND_TAKEN",
        "PEBS": "1",
        "PublicDescription": "Counts taken conditional branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Far branch instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.FAR_BRANCH",
        "PEBS": "1",
        "PublicDescription": "Counts far branch instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Indirect near branch instructions retired (excluding returns)",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.INDIRECT",
        "PEBS": "1",
        "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Direct and indirect near call instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.NEAR_CALL",
        "PEBS": "1",
        "PublicDescription": "Counts both direct and indirect near call instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Return instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.NEAR_RETURN",
        "PEBS": "1",
        "PublicDescription": "Counts return instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Taken branch instructions retired.",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
        "PEBS": "1",
        "PublicDescription": "Counts taken branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "All mispredicted branch instructions retired.",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "PEBS": "1",
        "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
        "SampleAfterValue": "400009"
    },
    {
        "BriefDescription": "Mispredicted conditional branch instructions retired.",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.COND",
        "PEBS": "1",
        "PublicDescription": "Counts mispredicted conditional branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x11"
    },
    {
        "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.COND_NTAKEN",
        "PEBS": "1",
        "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
        "SampleAfterValue": "400009",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.COND_TAKEN",
        "PEBS": "1",
        "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.INDIRECT",
        "PEBS": "1",
        "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Mispredicted indirect CALL retired.",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
        "PEBS": "1",
        "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
        "SampleAfterValue": "400009",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
        "PEBS": "1",
        "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
        "SampleAfterValue": "400009",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.RET",
        "PEBS": "1",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
        "EventCode": "0xec",
        "EventName": "CPU_CLK_UNHALTED.C01",
        "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
        "EventCode": "0xec",
        "EventName": "CPU_CLK_UNHALTED.C02",
        "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions.",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
        "EventCode": "0xec",
        "EventName": "CPU_CLK_UNHALTED.C0_WAIT",
        "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
        "SampleAfterValue": "2000003",
        "UMask": "0x70"
    },
    {
        "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
        "EventCode": "0xec",
        "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
        "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
        "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
        "SampleAfterValue": "25003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
        "EventCode": "0xec",
        "EventName": "CPU_CLK_UNHALTED.PAUSE",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xec",
        "EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
        "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Reference cycles when the core is not in halt state.",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
        "SampleAfterValue": "2000003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "Reference cycles when the core is not in halt state.",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
        "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Core cycles when the thread is not in halt state",
        "EventName": "CPU_CLK_UNHALTED.THREAD",
        "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Thread cycles when thread is not in halt state",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
        "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
        "SampleAfterValue": "2000003"
    },
    {
        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
        "CounterMask": "8",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
        "CounterMask": "1",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
        "CounterMask": "16",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
        "SampleAfterValue": "1000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
        "CounterMask": "12",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0xc"
    },
    {
        "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
        "CounterMask": "5",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x5"
    },
    {
        "BriefDescription": "Total execution stalls.",
        "CounterMask": "4",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
        "EventCode": "0xa6",
        "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
        "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
        "EventCode": "0xa6",
        "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
        "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
        "EventCode": "0xa6",
        "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
        "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
        "EventCode": "0xa6",
        "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
        "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
        "CounterMask": "5",
        "EventCode": "0xa6",
        "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
        "SampleAfterValue": "2000003",
        "UMask": "0x21"
    },
    {
        "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
        "CounterMask": "2",
        "EventCode": "0xa6",
        "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
        "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
        "SampleAfterValue": "1000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
        "EventCode": "0xa6",
        "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
        "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
        "SampleAfterValue": "1000003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Instruction decoders utilized in a cycle",
        "EventCode": "0x75",
        "EventName": "INST_DECODED.DECODERS",
        "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
        "EventName": "INST_RETIRED.ANY",
        "PEBS": "1",
        "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of instructions retired. General Counter - architectural event",
        "EventCode": "0xc0",
        "EventName": "INST_RETIRED.ANY_P",
        "PEBS": "1",
        "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
        "SampleAfterValue": "2000003"
    },
    {
        "BriefDescription": "INST_RETIRED.MACRO_FUSED",
        "EventCode": "0xc0",
        "EventName": "INST_RETIRED.MACRO_FUSED",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Retired NOP instructions.",
        "EventCode": "0xc0",
        "EventName": "INST_RETIRED.NOP",
        "PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
        "EventName": "INST_RETIRED.PREC_DIST",
        "PEBS": "1",
        "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Iterations of Repeat string retired instructions.",
        "EventCode": "0xc0",
        "EventName": "INST_RETIRED.REP_ITERATION",
        "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Clears speculative count",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xad",
        "EventName": "INT_MISC.CLEARS_COUNT",
        "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears",
        "SampleAfterValue": "500009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
        "EventCode": "0xad",
        "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
        "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
        "SampleAfterValue": "500009",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "INT_MISC.MBA_STALLS",
        "EventCode": "0xad",
        "EventName": "INT_MISC.MBA_STALLS",
        "SampleAfterValue": "1000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
        "EventCode": "0xad",
        "EventName": "INT_MISC.RECOVERY_CYCLES",
        "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
        "SampleAfterValue": "500009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
        "EventCode": "0xad",
        "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x7",
        "SampleAfterValue": "1000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "TMA slots where uops got dropped",
        "EventCode": "0xad",
        "EventName": "INT_MISC.UOP_DROPPING",
        "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
        "SampleAfterValue": "1000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "INT_VEC_RETIRED.128BIT",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.128BIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x13"
    },
    {
        "BriefDescription": "INT_VEC_RETIRED.256BIT",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.256BIT",
        "SampleAfterValue": "1000003",
        "UMask": "0xac"
    },
    {
        "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.ADD_128",
        "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.",
        "SampleAfterValue": "1000003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.ADD_256",
        "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.",
        "SampleAfterValue": "1000003",
        "UMask": "0xc"
    },
    {
        "BriefDescription": "INT_VEC_RETIRED.MUL_256",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.MUL_256",
        "SampleAfterValue": "1000003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "INT_VEC_RETIRED.SHUFFLES",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.SHUFFLES",
        "SampleAfterValue": "1000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "INT_VEC_RETIRED.VNNI_128",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.VNNI_128",
        "SampleAfterValue": "1000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "INT_VEC_RETIRED.VNNI_256",
        "EventCode": "0xe7",
        "EventName": "INT_VEC_RETIRED.VNNI_256",
        "SampleAfterValue": "1000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "False dependencies in MOB due to partial compare on address.",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.ADDRESS_ALIAS",
        "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.NO_SR",
        "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
        "SampleAfterValue": "100003",
        "UMask": "0x88"
    },
    {
        "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.STORE_FORWARD",
        "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
        "SampleAfterValue": "100003",
        "UMask": "0x82"
    },
    {
        "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
        "EventCode": "0x4c",
        "EventName": "LOAD_HIT_PREFETCH.SWPF",
        "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
        "CounterMask": "1",
        "EventCode": "0xa8",
        "EventName": "LSD.CYCLES_ACTIVE",
        "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
        "CounterMask": "6",
        "EventCode": "0xa8",
        "EventName": "LSD.CYCLES_OK",
        "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of Uops delivered by the LSD.",
        "EventCode": "0xa8",
        "EventName": "LSD.UOPS",
        "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of machine clears (nukes) of any type.",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.COUNT",
        "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Self-modifying code (SMC) detected.",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.SMC",
        "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "LFENCE instructions retired",
        "EventCode": "0xe0",
        "EventName": "MISC2_RETIRED.LFENCE",
        "PublicDescription": "number of LFENCE retired instructions",
        "SampleAfterValue": "400009",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Increments whenever there is an update to the LBR array.",
        "EventCode": "0xcc",
        "EventName": "MISC_RETIRED.LBR_INSERTS",
        "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
        "EventCode": "0xa2",
        "EventName": "RESOURCE_STALLS.SB",
        "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
        "EventCode": "0xa2",
        "EventName": "RESOURCE_STALLS.SCOREBOARD",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
        "PublicDescription": "Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
        "SampleAfterValue": "10000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "TMA slots wasted due to incorrect speculations.",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN.BAD_SPEC_SLOTS",
        "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.",
        "SampleAfterValue": "10000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
        "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
        "SampleAfterValue": "10000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS",
        "SampleAfterValue": "10000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
        "EventName": "TOPDOWN.SLOTS",
        "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
        "SampleAfterValue": "10000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN.SLOTS_P",
        "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
        "SampleAfterValue": "10000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "UOPS_DECODED.DEC0_UOPS",
        "EventCode": "0x76",
        "EventName": "UOPS_DECODED.DEC0_UOPS",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Uops executed on port 0",
        "EventCode": "0xb2",
        "EventName": "UOPS_DISPATCHED.PORT_0",
        "PublicDescription": "Number of uops dispatch to execution  port 0.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Uops executed on port 1",
        "EventCode": "0xb2",
        "EventName": "UOPS_DISPATCHED.PORT_1",
        "PublicDescription": "Number of uops dispatch to execution  port 1.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Uops executed on ports 2, 3 and 10",
        "EventCode": "0xb2",
        "EventName": "UOPS_DISPATCHED.PORT_2_3_10",
        "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Uops executed on ports 4 and 9",
        "EventCode": "0xb2",
        "EventName": "UOPS_DISPATCHED.PORT_4_9",
        "PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Uops executed on ports 5 and 11",
        "EventCode": "0xb2",
        "EventName": "UOPS_DISPATCHED.PORT_5_11",
        "PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Uops executed on port 6",
        "EventCode": "0xb2",
        "EventName": "UOPS_DISPATCHED.PORT_6",
        "PublicDescription": "Number of uops dispatch to execution  port 6.",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Uops executed on ports 7 and 8",
        "EventCode": "0xb2",
        "EventName": "UOPS_DISPATCHED.PORT_7_8",
        "PublicDescription": "Number of uops dispatch to execution  ports 7 and 8.",
        "SampleAfterValue": "2000003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Number of uops executed on the core.",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE",
        "PublicDescription": "Counts the number of uops executed from any thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
        "CounterMask": "1",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
        "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
        "CounterMask": "2",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
        "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
        "CounterMask": "3",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
        "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
        "CounterMask": "4",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
        "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
        "CounterMask": "1",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_1",
        "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
        "CounterMask": "2",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_2",
        "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
        "CounterMask": "3",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_3",
        "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
        "CounterMask": "4",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_4",
        "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
        "CounterMask": "1",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.STALLS",
        "Invert": "1",
        "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS",
        "CounterMask": "1",
        "Deprecated": "1",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.STALL_CYCLES",
        "Invert": "1",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.THREAD",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of x87 uops dispatched.",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.X87",
        "PublicDescription": "Counts the number of x87 uops executed.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Uops that RAT issues to RS",
        "EventCode": "0xae",
        "EventName": "UOPS_ISSUED.ANY",
        "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with retired uop(s).",
        "CounterMask": "1",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.CYCLES",
        "PublicDescription": "Counts cycles where at least one uop has retired.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Retired uops except the last uop of each instruction.",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.HEAVY",
        "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "UOPS_RETIRED.MS",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.MS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x8",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Retirement slots used.",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.SLOTS",
        "PublicDescription": "Counts the retirement slots used each cycle.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles without actually retired uops.",
        "CounterMask": "1",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.STALLS",
        "Invert": "1",
        "PublicDescription": "This event counts cycles without actually retired uops.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS",
        "CounterMask": "1",
        "Deprecated": "1",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.STALL_CYCLES",
        "Invert": "1",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    }
]