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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 | // SPDX-License-Identifier: GPL-2.0 /***************************************************************************/ /* * sltimers.c -- generic ColdFire slice timer support. * * Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be> * based on * timers.c -- generic ColdFire hardware timer support. * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com> */ /***************************************************************************/ #include <linux/kernel.h> #include <linux/init.h> #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/profile.h> #include <linux/clocksource.h> #include <asm/io.h> #include <asm/traps.h> #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfslt.h> #include <asm/mcfsim.h> /***************************************************************************/ #ifdef CONFIG_HIGHPROFILE /* * By default use Slice Timer 1 as the profiler clock timer. */ #define PA(a) (MCFSLT_TIMER1 + (a)) /* * Choose a reasonably fast profile timer. Make it an odd value to * try and get good coverage of kernel operations. */ #define PROFILEHZ 1013 irqreturn_t mcfslt_profile_tick(int irq, void *dummy) { /* Reset Slice Timer 1 */ __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR)); if (current->pid) profile_tick(CPU_PROFILING); return IRQ_HANDLED; } void mcfslt_profile_init(void) { int ret; printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n", PROFILEHZ); ret = request_irq(MCF_IRQ_PROFILER, mcfslt_profile_tick, IRQF_TIMER, "profile timer", NULL); if (ret) { pr_err("Failed to request irq %d (profile timer): %pe\n", MCF_IRQ_PROFILER, ERR_PTR(ret)); } /* Set up TIMER 2 as high speed profile clock */ __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT)); __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, PA(MCFSLT_SCR)); } #endif /* CONFIG_HIGHPROFILE */ /***************************************************************************/ /* * By default use Slice Timer 0 as the system clock timer. */ #define TA(a) (MCFSLT_TIMER0 + (a)) static u32 mcfslt_cycles_per_jiffy; static u32 mcfslt_cnt; static irqreturn_t mcfslt_tick(int irq, void *dummy) { /* Reset Slice Timer 0 */ __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR)); mcfslt_cnt += mcfslt_cycles_per_jiffy; legacy_timer_tick(1); return IRQ_HANDLED; } static u64 mcfslt_read_clk(struct clocksource *cs) { unsigned long flags; u32 cycles, scnt; local_irq_save(flags); scnt = __raw_readl(TA(MCFSLT_SCNT)); cycles = mcfslt_cnt; if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) { cycles += mcfslt_cycles_per_jiffy; scnt = __raw_readl(TA(MCFSLT_SCNT)); } local_irq_restore(flags); /* subtract because slice timers count down */ return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt); } static struct clocksource mcfslt_clk = { .name = "slt", .rating = 250, .read = mcfslt_read_clk, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; void hw_timer_init(void) { int r; mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ; /* * The coldfire slice timer (SLT) runs from STCNT to 0 included, * then STCNT again and so on. It counts thus actually * STCNT + 1 steps for 1 tick, not STCNT. So if you want * n cycles, initialize STCNT with n - 1. */ __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT)); __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, TA(MCFSLT_SCR)); /* initialize mcfslt_cnt knowing that slice timers count down */ mcfslt_cnt = mcfslt_cycles_per_jiffy; r = request_irq(MCF_IRQ_TIMER, mcfslt_tick, IRQF_TIMER, "timer", NULL); if (r) { pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER, ERR_PTR(r)); } clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK); #ifdef CONFIG_HIGHPROFILE mcfslt_profile_init(); #endif } |