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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/dsa/qca8k.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Atheros QCA83xx switch family maintainers: - John Crispin <john@phrozen.org> description: If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode describing a port needs to have a valid phandle referencing the internal PHY it is connected to. This is because there is no N:N mapping of port and PHY ID. To declare the internal mdio-bus configuration, declare an MDIO node in the switch node and declare the phandle for the port, referencing the internal PHY it is connected to. In this config, an internal mdio-bus is registered and the MDIO master is used for communication. Mixed external and internal mdio-bus configurations are not supported by the hardware. Each phy has at most 3 LEDs connected and can be declared using the standard LEDs structure. properties: compatible: oneOf: - enum: - qca,qca8327 - qca,qca8328 - qca,qca8334 - qca,qca8337 description: | qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package reg: maxItems: 1 reset-gpios: description: GPIO to be used to reset the whole device maxItems: 1 qca,ignore-power-on-sel: $ref: /schemas/types.yaml#/definitions/flag description: Ignore power-on pin strapping to configure LED open-drain or EEPROM presence. This is needed for devices with incorrect configuration or when the OEM has decided not to use pin strapping and falls back to SW regs. qca,led-open-drain: $ref: /schemas/types.yaml#/definitions/flag description: Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to be set, otherwise the driver will fail at probe. This is required if the OEM does not use pin strapping to set this mode and prefers to set it using SW regs. The pin strappings related to LED open-drain mode are B68 on the QCA832x and B49 on the QCA833x. mdio: $ref: /schemas/net/mdio.yaml# unevaluatedProperties: false description: Qca8k switch have an internal mdio to access switch port. If this is not present, the legacy mapping is used and the internal mdio access is used. With the legacy mapping the reg corresponding to the internal mdio is the switch reg with an offset of -1. $ref: dsa.yaml# patternProperties: "^(ethernet-)?ports$": type: object patternProperties: "^(ethernet-)?port@[0-6]$": type: object description: Ethernet switch ports $ref: dsa-port.yaml# properties: qca,sgmii-rxclk-falling-edge: $ref: /schemas/types.yaml#/definitions/flag description: Set the receive clock phase to falling edge. Mostly commonly used on the QCA8327 with CPU port 0 set to SGMII. qca,sgmii-txclk-falling-edge: $ref: /schemas/types.yaml#/definitions/flag description: Set the transmit clock phase to falling edge. qca,sgmii-enable-pll: $ref: /schemas/types.yaml#/definitions/flag description: For SGMII CPU port, explicitly enable PLL, TX and RX chain along with Signal Detection. On the QCA8327 this should not be enabled, otherwise the SGMII port will not initialize. When used on the QCA8337, revision 3 or greater, a warning will be displayed. When the CPU port is set to SGMII on the QCA8337, it is advised to set this unless a communication issue is observed. unevaluatedProperties: false oneOf: - required: - ports - required: - ethernet-ports required: - compatible - reg unevaluatedProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> mdio { #address-cells = <1>; #size-cells = <0>; external_phy_port1: ethernet-phy@0 { reg = <0>; }; external_phy_port2: ethernet-phy@1 { reg = <1>; }; external_phy_port3: ethernet-phy@2 { reg = <2>; }; external_phy_port4: ethernet-phy@3 { reg = <3>; }; external_phy_port5: ethernet-phy@4 { reg = <4>; }; switch@10 { compatible = "qca,qca8337"; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; reg = <0x10>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; ethernet = <&gmac1>; phy-mode = "rgmii"; fixed-link { speed = <1000>; full-duplex; }; }; port@1 { reg = <1>; label = "lan1"; phy-handle = <&external_phy_port1>; }; port@2 { reg = <2>; label = "lan2"; phy-handle = <&external_phy_port2>; }; port@3 { reg = <3>; label = "lan3"; phy-handle = <&external_phy_port3>; }; port@4 { reg = <4>; label = "lan4"; phy-handle = <&external_phy_port4>; }; port@5 { reg = <5>; label = "wan"; phy-handle = <&external_phy_port5>; }; }; }; }; - | #include <dt-bindings/gpio/gpio.h> mdio { #address-cells = <1>; #size-cells = <0>; switch@10 { compatible = "qca,qca8337"; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; reg = <0x10>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; ethernet = <&gmac1>; phy-mode = "rgmii"; fixed-link { speed = <1000>; full-duplex; }; }; port@1 { reg = <1>; label = "lan1"; phy-mode = "internal"; phy-handle = <&internal_phy_port1>; leds { #address-cells = <1>; #size-cells = <0>; led@0 { reg = <0>; color = <LED_COLOR_ID_WHITE>; function = LED_FUNCTION_LAN; default-state = "keep"; }; led@1 { reg = <1>; color = <LED_COLOR_ID_AMBER>; function = LED_FUNCTION_LAN; default-state = "keep"; }; }; }; port@2 { reg = <2>; label = "lan2"; phy-mode = "internal"; phy-handle = <&internal_phy_port2>; }; port@3 { reg = <3>; label = "lan3"; phy-mode = "internal"; phy-handle = <&internal_phy_port3>; }; port@4 { reg = <4>; label = "lan4"; phy-mode = "internal"; phy-handle = <&internal_phy_port4>; }; port@5 { reg = <5>; label = "wan"; phy-mode = "internal"; phy-handle = <&internal_phy_port5>; }; port@6 { reg = <0>; ethernet = <&gmac1>; phy-mode = "sgmii"; qca,sgmii-rxclk-falling-edge; fixed-link { speed = <1000>; full-duplex; }; }; }; mdio { #address-cells = <1>; #size-cells = <0>; internal_phy_port1: ethernet-phy@0 { reg = <0>; }; internal_phy_port2: ethernet-phy@1 { reg = <1>; }; internal_phy_port3: ethernet-phy@2 { reg = <2>; }; internal_phy_port4: ethernet-phy@3 { reg = <3>; }; internal_phy_port5: ethernet-phy@4 { reg = <4>; }; }; }; }; |