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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Unaligned memory access handler * * Copyright (C) 2001 Randolph Chung <tausq@debian.org> * Copyright (C) 2022 Helge Deller <deller@gmx.de> * Significantly tweaked by LaMont Jones <lamont@debian.org> */ #include <linux/sched/signal.h> #include <linux/signal.h> #include <linux/ratelimit.h> #include <linux/uaccess.h> #include <asm/hardirq.h> #include <asm/traps.h> /* #define DEBUG_UNALIGNED 1 */ #ifdef DEBUG_UNALIGNED #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0) #else #define DPRINTF(fmt, args...) #endif #define RFMT "%#08lx" /* 1111 1100 0000 0000 0001 0011 1100 0000 */ #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6) #define OPCODE2(a,b) ((a)<<26|(b)<<1) #define OPCODE3(a,b) ((a)<<26|(b)<<2) #define OPCODE4(a) ((a)<<26) #define OPCODE1_MASK OPCODE1(0x3f,1,0xf) #define OPCODE2_MASK OPCODE2(0x3f,1) #define OPCODE3_MASK OPCODE3(0x3f,1) #define OPCODE4_MASK OPCODE4(0x3f) /* skip LDB - never unaligned (index) */ #define OPCODE_LDH_I OPCODE1(0x03,0,0x1) #define OPCODE_LDW_I OPCODE1(0x03,0,0x2) #define OPCODE_LDD_I OPCODE1(0x03,0,0x3) #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4) #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5) #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6) #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7) /* skip LDB - never unaligned (short) */ #define OPCODE_LDH_S OPCODE1(0x03,1,0x1) #define OPCODE_LDW_S OPCODE1(0x03,1,0x2) #define OPCODE_LDD_S OPCODE1(0x03,1,0x3) #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4) #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5) #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6) #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7) /* skip STB - never unaligned */ #define OPCODE_STH OPCODE1(0x03,1,0x9) #define OPCODE_STW OPCODE1(0x03,1,0xa) #define OPCODE_STD OPCODE1(0x03,1,0xb) /* skip STBY - never unaligned */ /* skip STDBY - never unaligned */ #define OPCODE_STWA OPCODE1(0x03,1,0xe) #define OPCODE_STDA OPCODE1(0x03,1,0xf) #define OPCODE_FLDWX OPCODE1(0x09,0,0x0) #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1) #define OPCODE_FSTWX OPCODE1(0x09,0,0x8) #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9) #define OPCODE_FLDWS OPCODE1(0x09,1,0x0) #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1) #define OPCODE_FSTWS OPCODE1(0x09,1,0x8) #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9) #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0) #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8) #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0) #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8) #define OPCODE_LDD_L OPCODE2(0x14,0) #define OPCODE_FLDD_L OPCODE2(0x14,1) #define OPCODE_STD_L OPCODE2(0x1c,0) #define OPCODE_FSTD_L OPCODE2(0x1c,1) #define OPCODE_LDW_M OPCODE3(0x17,1) #define OPCODE_FLDW_L OPCODE3(0x17,0) #define OPCODE_FSTW_L OPCODE3(0x1f,0) #define OPCODE_STW_M OPCODE3(0x1f,1) #define OPCODE_LDH_L OPCODE4(0x11) #define OPCODE_LDW_L OPCODE4(0x12) #define OPCODE_LDWM OPCODE4(0x13) #define OPCODE_STH_L OPCODE4(0x19) #define OPCODE_STW_L OPCODE4(0x1A) #define OPCODE_STWM OPCODE4(0x1B) #define MAJOR_OP(i) (((i)>>26)&0x3f) #define R1(i) (((i)>>21)&0x1f) #define R2(i) (((i)>>16)&0x1f) #define R3(i) ((i)&0x1f) #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1)) #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0)) #define IM5_2(i) IM((i)>>16,5) #define IM5_3(i) IM((i),5) #define IM14(i) IM((i),14) #define ERR_NOTHANDLED -1 int unaligned_enabled __read_mostly = 1; static int emulate_ldh(struct pt_regs *regs, int toreg) { unsigned long saddr = regs->ior; unsigned long val = 0, temp1; ASM_EXCEPTIONTABLE_VAR(ret); DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n", regs->isr, regs->ior, toreg); __asm__ __volatile__ ( " mtsp %4, %%sr1\n" "1: ldbs 0(%%sr1,%3), %2\n" "2: ldbs 1(%%sr1,%3), %0\n" " depw %2, 23, 24, %0\n" "3: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) : "+r" (val), "+r" (ret), "=&r" (temp1) : "r" (saddr), "r" (regs->isr) ); DPRINTF("val = " RFMT "\n", val); if (toreg) regs->gr[toreg] = val; return ret; } static int emulate_ldw(struct pt_regs *regs, int toreg, int flop) { unsigned long saddr = regs->ior; unsigned long val = 0, temp1, temp2; ASM_EXCEPTIONTABLE_VAR(ret); DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n", regs->isr, regs->ior, toreg); __asm__ __volatile__ ( " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */ " mtsp %5, %%sr1\n" " depw %%r0,31,2,%4\n" "1: ldw 0(%%sr1,%4),%0\n" "2: ldw 4(%%sr1,%4),%3\n" " subi 32,%2,%2\n" " mtctl %2,11\n" " vshd %0,%3,%0\n" "3: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2) : "r" (saddr), "r" (regs->isr) ); DPRINTF("val = " RFMT "\n", val); if (flop) ((__u32*)(regs->fr))[toreg] = val; else if (toreg) regs->gr[toreg] = val; return ret; } static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) { unsigned long saddr = regs->ior; __u64 val = 0; ASM_EXCEPTIONTABLE_VAR(ret); DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n", regs->isr, regs->ior, toreg); if (!IS_ENABLED(CONFIG_64BIT) && !flop) return ERR_NOTHANDLED; #ifdef CONFIG_64BIT __asm__ __volatile__ ( " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */ " mtsp %4, %%sr1\n" " depd %%r0,63,3,%3\n" "1: ldd 0(%%sr1,%3),%0\n" "2: ldd 8(%%sr1,%3),%%r20\n" " subi 64,%%r19,%%r19\n" " mtsar %%r19\n" " shrpd %0,%%r20,%%sar,%0\n" "3: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) : "=r" (val), "+r" (ret) : "0" (val), "r" (saddr), "r" (regs->isr) : "r19", "r20" ); #else { unsigned long shift, temp1; __asm__ __volatile__ ( " zdep %2,29,2,%3\n" /* r19=(ofs&3)*8 */ " mtsp %5, %%sr1\n" " dep %%r0,31,2,%2\n" "1: ldw 0(%%sr1,%2),%0\n" "2: ldw 4(%%sr1,%2),%R0\n" "3: ldw 8(%%sr1,%2),%4\n" " subi 32,%3,%3\n" " mtsar %3\n" " vshd %0,%R0,%0\n" " vshd %R0,%4,%R0\n" "4: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b) : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1) : "r" (regs->isr) ); } #endif DPRINTF("val = 0x%llx\n", val); if (flop) regs->fr[toreg] = val; else if (toreg) regs->gr[toreg] = val; return ret; } static int emulate_sth(struct pt_regs *regs, int frreg) { unsigned long val = regs->gr[frreg], temp1; ASM_EXCEPTIONTABLE_VAR(ret); if (!frreg) val = 0; DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg, val, regs->isr, regs->ior); __asm__ __volatile__ ( " mtsp %4, %%sr1\n" " extrw,u %2, 23, 8, %1\n" "1: stb %1, 0(%%sr1, %3)\n" "2: stb %2, 1(%%sr1, %3)\n" "3: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) : "+r" (ret), "=&r" (temp1) : "r" (val), "r" (regs->ior), "r" (regs->isr) ); return ret; } static int emulate_stw(struct pt_regs *regs, int frreg, int flop) { unsigned long val; ASM_EXCEPTIONTABLE_VAR(ret); if (flop) val = ((__u32*)(regs->fr))[frreg]; else if (frreg) val = regs->gr[frreg]; else val = 0; DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg, val, regs->isr, regs->ior); __asm__ __volatile__ ( " mtsp %3, %%sr1\n" " zdep %2, 28, 2, %%r19\n" " dep %%r0, 31, 2, %2\n" " mtsar %%r19\n" " depwi,z -2, %%sar, 32, %%r19\n" "1: ldw 0(%%sr1,%2),%%r20\n" "2: ldw 4(%%sr1,%2),%%r21\n" " vshd %%r0, %1, %%r22\n" " vshd %1, %%r0, %%r1\n" " and %%r20, %%r19, %%r20\n" " andcm %%r21, %%r19, %%r21\n" " or %%r22, %%r20, %%r20\n" " or %%r1, %%r21, %%r21\n" " stw %%r20,0(%%sr1,%2)\n" " stw %%r21,4(%%sr1,%2)\n" "3: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) : "+r" (ret) : "r" (val), "r" (regs->ior), "r" (regs->isr) : "r19", "r20", "r21", "r22", "r1" ); return ret; } static int emulate_std(struct pt_regs *regs, int frreg, int flop) { __u64 val; ASM_EXCEPTIONTABLE_VAR(ret); if (flop) val = regs->fr[frreg]; else if (frreg) val = regs->gr[frreg]; else val = 0; DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg, val, regs->isr, regs->ior); if (!IS_ENABLED(CONFIG_64BIT) && !flop) return ERR_NOTHANDLED; #ifdef CONFIG_64BIT __asm__ __volatile__ ( " mtsp %3, %%sr1\n" " depd,z %2, 60, 3, %%r19\n" " depd %%r0, 63, 3, %2\n" " mtsar %%r19\n" " depdi,z -2, %%sar, 64, %%r19\n" "1: ldd 0(%%sr1,%2),%%r20\n" "2: ldd 8(%%sr1,%2),%%r21\n" " shrpd %%r0, %1, %%sar, %%r22\n" " shrpd %1, %%r0, %%sar, %%r1\n" " and %%r20, %%r19, %%r20\n" " andcm %%r21, %%r19, %%r21\n" " or %%r22, %%r20, %%r20\n" " or %%r1, %%r21, %%r21\n" "3: std %%r20,0(%%sr1,%2)\n" "4: std %%r21,8(%%sr1,%2)\n" "5: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b) : "+r" (ret) : "r" (val), "r" (regs->ior), "r" (regs->isr) : "r19", "r20", "r21", "r22", "r1" ); #else { unsigned long valh=(val>>32),vall=(val&0xffffffffl); __asm__ __volatile__ ( " mtsp %4, %%sr1\n" " zdep %2, 29, 2, %%r19\n" " dep %%r0, 31, 2, %3\n" " mtsar %%r19\n" " zvdepi -2, 32, %%r19\n" "1: ldw 0(%%sr1,%3),%%r20\n" "2: ldw 8(%%sr1,%3),%%r21\n" " vshd %1, %2, %%r1\n" " vshd %%r0, %1, %1\n" " vshd %2, %%r0, %2\n" " and %%r20, %%r19, %%r20\n" " andcm %%r21, %%r19, %%r21\n" " or %1, %%r20, %1\n" " or %2, %%r21, %2\n" "3: stw %1,0(%%sr1,%3)\n" "4: stw %%r1,4(%%sr1,%3)\n" "5: stw %2,8(%%sr1,%3)\n" "6: \n" ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b) ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b) : "+r" (ret) : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr) : "r19", "r20", "r21", "r1" ); } #endif return ret; } void handle_unaligned(struct pt_regs *regs) { static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5); unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; int modify = 0; int ret = ERR_NOTHANDLED; __inc_irq_stat(irq_unaligned_count); /* log a message with pacing */ if (user_mode(regs)) { if (current->thread.flags & PARISC_UAC_SIGBUS) { goto force_sigbus; } if (!(current->thread.flags & PARISC_UAC_NOPRINT) && __ratelimit(&ratelimit)) { printk(KERN_WARNING "%s(%d): unaligned access to " RFMT " at ip " RFMT " (iir " RFMT ")\n", current->comm, task_pid_nr(current), regs->ior, regs->iaoq[0], regs->iir); #ifdef DEBUG_UNALIGNED show_regs(regs); #endif } if (!unaligned_enabled) goto force_sigbus; } /* handle modification - OK, it's ugly, see the instruction manual */ switch (MAJOR_OP(regs->iir)) { case 0x03: case 0x09: case 0x0b: if (regs->iir&0x20) { modify = 1; if (regs->iir&0x1000) /* short loads */ if (regs->iir&0x200) newbase += IM5_3(regs->iir); else newbase += IM5_2(regs->iir); else if (regs->iir&0x2000) /* scaled indexed */ { int shift=0; switch (regs->iir & OPCODE1_MASK) { case OPCODE_LDH_I: shift= 1; break; case OPCODE_LDW_I: shift= 2; break; case OPCODE_LDD_I: case OPCODE_LDDA_I: shift= 3; break; } newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; } else /* simple indexed */ newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); } break; case 0x13: case 0x1b: modify = 1; newbase += IM14(regs->iir); break; case 0x14: case 0x1c: if (regs->iir&8) { modify = 1; newbase += IM14(regs->iir&~0xe); } break; case 0x16: case 0x1e: modify = 1; newbase += IM14(regs->iir&6); break; case 0x17: case 0x1f: if (regs->iir&4) { modify = 1; newbase += IM14(regs->iir&~4); } break; } /* TODO: make this cleaner... */ switch (regs->iir & OPCODE1_MASK) { case OPCODE_LDH_I: case OPCODE_LDH_S: ret = emulate_ldh(regs, R3(regs->iir)); break; case OPCODE_LDW_I: case OPCODE_LDWA_I: case OPCODE_LDW_S: case OPCODE_LDWA_S: ret = emulate_ldw(regs, R3(regs->iir),0); break; case OPCODE_STH: ret = emulate_sth(regs, R2(regs->iir)); break; case OPCODE_STW: case OPCODE_STWA: ret = emulate_stw(regs, R2(regs->iir),0); break; #ifdef CONFIG_64BIT case OPCODE_LDD_I: case OPCODE_LDDA_I: case OPCODE_LDD_S: case OPCODE_LDDA_S: ret = emulate_ldd(regs, R3(regs->iir),0); break; case OPCODE_STD: case OPCODE_STDA: ret = emulate_std(regs, R2(regs->iir),0); break; #endif case OPCODE_FLDWX: case OPCODE_FLDWS: case OPCODE_FLDWXR: case OPCODE_FLDWSR: ret = emulate_ldw(regs,FR3(regs->iir),1); break; case OPCODE_FLDDX: case OPCODE_FLDDS: ret = emulate_ldd(regs,R3(regs->iir),1); break; case OPCODE_FSTWX: case OPCODE_FSTWS: case OPCODE_FSTWXR: case OPCODE_FSTWSR: ret = emulate_stw(regs,FR3(regs->iir),1); break; case OPCODE_FSTDX: case OPCODE_FSTDS: ret = emulate_std(regs,R3(regs->iir),1); break; case OPCODE_LDCD_I: case OPCODE_LDCW_I: case OPCODE_LDCD_S: case OPCODE_LDCW_S: ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */ break; } switch (regs->iir & OPCODE2_MASK) { case OPCODE_FLDD_L: ret = emulate_ldd(regs,R2(regs->iir),1); break; case OPCODE_FSTD_L: ret = emulate_std(regs, R2(regs->iir),1); break; #ifdef CONFIG_64BIT case OPCODE_LDD_L: ret = emulate_ldd(regs, R2(regs->iir),0); break; case OPCODE_STD_L: ret = emulate_std(regs, R2(regs->iir),0); break; #endif } switch (regs->iir & OPCODE3_MASK) { case OPCODE_FLDW_L: ret = emulate_ldw(regs, R2(regs->iir), 1); break; case OPCODE_LDW_M: ret = emulate_ldw(regs, R2(regs->iir), 0); break; case OPCODE_FSTW_L: ret = emulate_stw(regs, R2(regs->iir),1); break; case OPCODE_STW_M: ret = emulate_stw(regs, R2(regs->iir),0); break; } switch (regs->iir & OPCODE4_MASK) { case OPCODE_LDH_L: ret = emulate_ldh(regs, R2(regs->iir)); break; case OPCODE_LDW_L: case OPCODE_LDWM: ret = emulate_ldw(regs, R2(regs->iir),0); break; case OPCODE_STH_L: ret = emulate_sth(regs, R2(regs->iir)); break; case OPCODE_STW_L: case OPCODE_STWM: ret = emulate_stw(regs, R2(regs->iir),0); break; } if (ret == 0 && modify && R1(regs->iir)) regs->gr[R1(regs->iir)] = newbase; if (ret == ERR_NOTHANDLED) printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir); DPRINTF("ret = %d\n", ret); if (ret) { /* * The unaligned handler failed. * If we were called by __get_user() or __put_user() jump * to it's exception fixup handler instead of crashing. */ if (!user_mode(regs) && fixup_exception(regs)) return; printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret); die_if_kernel("Unaligned data reference", regs, 28); if (ret == -EFAULT) { force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)regs->ior); } else { force_sigbus: /* couldn't handle it ... */ force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->ior); } return; } /* else we handled it, let life go on. */ regs->gr[0]|=PSW_N; } /* * NB: check_unaligned() is only used for PCXS processors right * now, so we only check for PA1.1 encodings at this point. */ int check_unaligned(struct pt_regs *regs) { unsigned long align_mask; /* Get alignment mask */ align_mask = 0UL; switch (regs->iir & OPCODE1_MASK) { case OPCODE_LDH_I: case OPCODE_LDH_S: case OPCODE_STH: align_mask = 1UL; break; case OPCODE_LDW_I: case OPCODE_LDWA_I: case OPCODE_LDW_S: case OPCODE_LDWA_S: case OPCODE_STW: case OPCODE_STWA: align_mask = 3UL; break; default: switch (regs->iir & OPCODE4_MASK) { case OPCODE_LDH_L: case OPCODE_STH_L: align_mask = 1UL; break; case OPCODE_LDW_L: case OPCODE_LDWM: case OPCODE_STW_L: case OPCODE_STWM: align_mask = 3UL; break; } break; } return (int)(regs->ior & align_mask); } |