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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 | /* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "reg_helper.h" #include "core_types.h" #include "dcn31_dccg.h" #include "dal_asic_id.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) #define REG(reg) \ (dccg_dcn->regs->reg) #undef FN #define FN(reg_name, field_name) \ dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name #define CTX \ dccg_dcn->base.ctx #define DC_LOGGER \ dccg->ctx->logger void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); if (dccg->ref_dppclk && req_dppclk) { int ref_dppclk = dccg->ref_dppclk; int modulo, phase; // phase / modulo = dpp pipe clk / dpp global clk modulo = 0xff; // use FF at the end phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; if (phase > 0xff) { ASSERT(false); phase = 0xff; } REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, DPPCLK0_DTO_PHASE, phase, DPPCLK0_DTO_MODULO, modulo); REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1); } else { REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0); } dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; } static enum phyd32clk_clock_source get_phy_mux_symclk( struct dcn_dccg *dccg_dcn, enum phyd32clk_clock_source src) { if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { if (src == PHYD32CLKC) src = PHYD32CLKF; if (src == PHYD32CLKD) src = PHYD32CLKG; } return src; } static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); /* enabled to select one of the DTBCLKs for pipe */ switch (otg_inst) { case 0: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, 1); break; case 1: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, 1); break; case 2: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, 1); break; case 3: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, 1); break; default: BREAK_TO_DEBUGGER(); return; } if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, 1, DPSTREAMCLK_ROOT_GATE_DISABLE, 1); } static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, 0, DPSTREAMCLK_GATE_DISABLE, 0); switch (otg_inst) { case 0: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, 0); break; case 1: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, 0); break; case 2: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, 0); break; case 3: REG_UPDATE(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, 0); break; default: BREAK_TO_DEBUGGER(); return; } } void dccg31_set_dpstreamclk( struct dccg *dccg, enum streamclk_source src, int otg_inst, int dp_hpo_inst) { if (src == REFCLK) dccg31_disable_dpstreamclk(dccg, otg_inst); else dccg31_enable_dpstreamclk(dccg, otg_inst); } void dccg31_enable_symclk32_se( struct dccg *dccg, int hpo_se_inst, enum phyd32clk_clock_source phyd32clk) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk); /* select one of the PHYD32CLKs as the source for symclk32_se */ switch (hpo_se_inst) { case 0: if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, 1, SYMCLK32_ROOT_SE0_GATE_DISABLE, 1); REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, phyd32clk, SYMCLK32_SE0_EN, 1); break; case 1: if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, 1, SYMCLK32_ROOT_SE1_GATE_DISABLE, 1); REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, phyd32clk, SYMCLK32_SE1_EN, 1); break; case 2: if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, 1, SYMCLK32_ROOT_SE2_GATE_DISABLE, 1); REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, phyd32clk, SYMCLK32_SE2_EN, 1); break; case 3: if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, 1, SYMCLK32_ROOT_SE3_GATE_DISABLE, 1); REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, phyd32clk, SYMCLK32_SE3_EN, 1); break; default: BREAK_TO_DEBUGGER(); return; } } void dccg31_disable_symclk32_se( struct dccg *dccg, int hpo_se_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); /* set refclk as the source for symclk32_se */ switch (hpo_se_inst) { case 0: REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, 0, SYMCLK32_SE0_EN, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, 0, SYMCLK32_ROOT_SE0_GATE_DISABLE, 0); break; case 1: REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, 0, SYMCLK32_SE1_EN, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, 0, SYMCLK32_ROOT_SE1_GATE_DISABLE, 0); break; case 2: REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, 0, SYMCLK32_SE2_EN, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, 0, SYMCLK32_ROOT_SE2_GATE_DISABLE, 0); break; case 3: REG_UPDATE_2(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, 0, SYMCLK32_SE3_EN, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, 0, SYMCLK32_ROOT_SE3_GATE_DISABLE, 0); break; default: BREAK_TO_DEBUGGER(); return; } } void dccg31_enable_symclk32_le( struct dccg *dccg, int hpo_le_inst, enum phyd32clk_clock_source phyd32clk) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk); /* select one of the PHYD32CLKs as the source for symclk32_le */ switch (hpo_le_inst) { case 0: if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, 1, SYMCLK32_ROOT_LE0_GATE_DISABLE, 1); REG_UPDATE_2(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, phyd32clk, SYMCLK32_LE0_EN, 1); break; case 1: if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, 1, SYMCLK32_ROOT_LE1_GATE_DISABLE, 1); REG_UPDATE_2(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, phyd32clk, SYMCLK32_LE1_EN, 1); break; default: BREAK_TO_DEBUGGER(); return; } } void dccg31_disable_symclk32_le( struct dccg *dccg, int hpo_le_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); /* set refclk as the source for symclk32_le */ switch (hpo_le_inst) { case 0: REG_UPDATE_2(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, 0, SYMCLK32_LE0_EN, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, 0, SYMCLK32_ROOT_LE0_GATE_DISABLE, 0); break; case 1: REG_UPDATE_2(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, 0, SYMCLK32_LE1_EN, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, 0, SYMCLK32_ROOT_LE1_GATE_DISABLE, 0); break; default: BREAK_TO_DEBUGGER(); return; } } void dccg31_disable_dscclk(struct dccg *dccg, int inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) return; //DTO must be enabled to generate a 0 Hz clock output switch (inst) { case 0: REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, 1); REG_UPDATE_2(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, 0, DSCCLK0_DTO_MODULO, 1); break; case 1: REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, 1); REG_UPDATE_2(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, 0, DSCCLK1_DTO_MODULO, 1); break; case 2: REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, 1); REG_UPDATE_2(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, 0, DSCCLK2_DTO_MODULO, 1); break; case 3: if (REG(DSCCLK3_DTO_PARAM)) { REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_DTO_ENABLE, 1); REG_UPDATE_2(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, 0, DSCCLK3_DTO_MODULO, 1); } break; default: BREAK_TO_DEBUGGER(); return; } } void dccg31_enable_dscclk(struct dccg *dccg, int inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) return; //Disable DTO switch (inst) { case 0: REG_UPDATE_2(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, 0, DSCCLK0_DTO_MODULO, 0); REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, 0); break; case 1: REG_UPDATE_2(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, 0, DSCCLK1_DTO_MODULO, 0); REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, 0); break; case 2: REG_UPDATE_2(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, 0, DSCCLK2_DTO_MODULO, 0); REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, 0); break; case 3: if (REG(DSCCLK3_DTO_PARAM)) { REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_DTO_ENABLE, 0); REG_UPDATE_2(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, 0, DSCCLK3_DTO_MODULO, 0); } break; default: BREAK_TO_DEBUGGER(); return; } } void dccg31_set_physymclk( struct dccg *dccg, int phy_inst, enum physymclk_clock_source clk_src, bool force_enable) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); /* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */ switch (phy_inst) { case 0: if (force_enable) { REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, 1, PHYASYMCLK_FORCE_SRC_SEL, clk_src); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, 1); } else { REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, 0, PHYASYMCLK_FORCE_SRC_SEL, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, 0); } break; case 1: if (force_enable) { REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, 1, PHYBSYMCLK_FORCE_SRC_SEL, clk_src); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, 1); } else { REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, 0, PHYBSYMCLK_FORCE_SRC_SEL, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, 0); } break; case 2: if (force_enable) { REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, 1, PHYCSYMCLK_FORCE_SRC_SEL, clk_src); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, 1); } else { REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, 0, PHYCSYMCLK_FORCE_SRC_SEL, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, 0); } break; case 3: if (force_enable) { REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, 1, PHYDSYMCLK_FORCE_SRC_SEL, clk_src); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, 1); } else { REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, 0, PHYDSYMCLK_FORCE_SRC_SEL, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, 0); } break; case 4: if (force_enable) { REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, 1, PHYESYMCLK_FORCE_SRC_SEL, clk_src); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, 1); } else { REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, 0, PHYESYMCLK_FORCE_SRC_SEL, 0); if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, 0); } break; default: BREAK_TO_DEBUGGER(); return; } } /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ void dccg31_set_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); int req_dtbclk_khz = params->pixclk_khz; uint32_t dtbdto_div; /* Mode DTBDTO Rate DTBCLK_DTO<x>_DIV Register * ODM 4:1 combine pixel rate/4 2 * ODM 2:1 combine pixel rate/2 4 * non-DSC 4:2:0 mode pixel rate/2 4 * DSC native 4:2:0 pixel rate/2 4 * DSC native 4:2:2 pixel rate/2 4 * Other modes pixel rate 8 */ if (params->num_odm_segments == 4) { dtbdto_div = 2; req_dtbclk_khz = params->pixclk_khz / 4; } else if ((params->num_odm_segments == 2) || (params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) || (params->timing->flags.DSC && params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && !params->timing->dsc_cfg.ycbcr422_simple)) { dtbdto_div = 4; req_dtbclk_khz = params->pixclk_khz / 2; } else dtbdto_div = 8; if (params->ref_dtbclk_khz && req_dtbclk_khz) { uint32_t modulo, phase; // phase / modulo = dtbclk / dtbclk ref modulo = params->ref_dtbclk_khz * 1000; phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), params->ref_dtbclk_khz); REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], DTBCLK_DTO_ENABLE[params->otg_inst], 1); REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, 1, 100); /* The recommended programming sequence to enable DTBCLK DTO to generate * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should * be set only after DTO is enabled */ REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], PIPE_DTO_SRC_SEL[params->otg_inst], 1); } else { REG_UPDATE_3(OTG_PIXEL_RATE_CNTL[params->otg_inst], DTBCLK_DTO_ENABLE[params->otg_inst], 0, PIPE_DTO_SRC_SEL[params->otg_inst], 0, DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); } } void dccg31_set_audio_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) { uint32_t modulo, phase; // phase / modulo = dtbclk / dtbclk ref modulo = params->ref_dtbclk_khz * 1000; phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), params->ref_dtbclk_khz); REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo); REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase); //REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, // DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO, 1); REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 4); // 04 - DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK } else { REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0); REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0); REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 3); // 03 - DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO } } void dccg31_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz) { /* * Assume refclk is sourced from xtalin * expect 24MHz */ *dccg_ref_freq_inKhz = xtalin_freq_inKhz; return; } void dccg31_set_dispclk_change_mode( struct dccg *dccg, enum dentist_dispclk_change_mode change_mode) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, change_mode == DISPCLK_CHANGE_MODE_RAMPING ? 2 : 0); } void dccg31_init(struct dccg *dccg) { /* Set HPO stream encoder to use refclk to avoid case where PHY is * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which * will cause DCN to hang. */ dccg31_disable_symclk32_se(dccg, 0); dccg31_disable_symclk32_se(dccg, 1); dccg31_disable_symclk32_se(dccg, 2); dccg31_disable_symclk32_se(dccg, 3); if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) { dccg31_disable_symclk32_le(dccg, 0); dccg31_disable_symclk32_le(dccg, 1); } if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) { dccg31_disable_dpstreamclk(dccg, 0); dccg31_disable_dpstreamclk(dccg, 1); dccg31_disable_dpstreamclk(dccg, 2); dccg31_disable_dpstreamclk(dccg, 3); } if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) { dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false); dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false); dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false); dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false); dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false); } } void dccg31_otg_add_pixel(struct dccg *dccg, uint32_t otg_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], OTG_ADD_PIXEL[otg_inst], 1); } void dccg31_otg_drop_pixel(struct dccg *dccg, uint32_t otg_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], OTG_DROP_PIXEL[otg_inst], 1); } static const struct dccg_funcs dccg31_funcs = { .update_dpp_dto = dccg31_update_dpp_dto, .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, .dccg_init = dccg31_init, .set_dpstreamclk = dccg31_set_dpstreamclk, .enable_symclk32_se = dccg31_enable_symclk32_se, .disable_symclk32_se = dccg31_disable_symclk32_se, .enable_symclk32_le = dccg31_enable_symclk32_le, .disable_symclk32_le = dccg31_disable_symclk32_le, .set_physymclk = dccg31_set_physymclk, .set_dtbclk_dto = dccg31_set_dtbclk_dto, .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg31_otg_add_pixel, .otg_drop_pixel = dccg31_otg_drop_pixel, .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, .disable_dsc = dccg31_disable_dscclk, .enable_dsc = dccg31_enable_dscclk, }; struct dccg *dccg31_create( struct dc_context *ctx, const struct dccg_registers *regs, const struct dccg_shift *dccg_shift, const struct dccg_mask *dccg_mask) { struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); struct dccg *base; if (dccg_dcn == NULL) { BREAK_TO_DEBUGGER(); return NULL; } base = &dccg_dcn->base; base->ctx = ctx; base->funcs = &dccg31_funcs; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; return &dccg_dcn->base; } |