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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 | // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2014 Linaro Ltd. * Copyright (c) 2013-2014 HiSilicon Limited. */ #include <dt-bindings/clock/hix5hd2-clock.h> / { #address-cells = <1>; #size-cells = <1>; aliases { serial0 = &uart0; }; gic: interrupt-controller@f8a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; /* gic dist base, gic cpu base */ reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&gic>; ranges = <0 0xf8000000 0x8000000>; amba-bus { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; timer0: timer@2000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00002000 0x1000>; /* timer00 & timer01 */ interrupts = <0 24 4>; clocks = <&clock HIX5HD2_FIXED_24M>; status = "disabled"; }; timer1: timer@a29000 { /* * Only used in NORMAL state, not available ins * SLOW or DOZE state. * The rate is fixed in 24MHz. */ compatible = "arm,sp804", "arm,primecell"; reg = <0x00a29000 0x1000>; /* timer10 & timer11 */ interrupts = <0 25 4>; clocks = <&clock HIX5HD2_FIXED_24M>; status = "disabled"; }; timer2: timer@a2a000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a2a000 0x1000>; /* timer20 & timer21 */ interrupts = <0 26 4>; clocks = <&clock HIX5HD2_FIXED_24M>; status = "disabled"; }; timer3: timer@a2b000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a2b000 0x1000>; /* timer30 & timer31 */ interrupts = <0 27 4>; clocks = <&clock HIX5HD2_FIXED_24M>; status = "disabled"; }; timer4: timer@a81000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a81000 0x1000>; /* timer30 & timer31 */ interrupts = <0 28 4>; clocks = <&clock HIX5HD2_FIXED_24M>; status = "disabled"; }; uart0: serial@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b00000 0x1000>; interrupts = <0 49 4>; clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; uart1: serial@6000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00006000 0x1000>; interrupts = <0 50 4>; clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; uart2: serial@b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b02000 0x1000>; interrupts = <0 51 4>; clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; uart3: serial@b03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b03000 0x1000>; interrupts = <0 52 4>; clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; uart4: serial@b04000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 53 4>; clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; gpio0: gpio@b20000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb20000 0x1000>; interrupts = <0 108 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio1: gpio@b21000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb21000 0x1000>; interrupts = <0 109 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio2: gpio@b22000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb22000 0x1000>; interrupts = <0 110 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio3: gpio@b23000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb23000 0x1000>; interrupts = <0 111 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio4: gpio@b24000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb24000 0x1000>; interrupts = <0 112 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio5: gpio@4000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x004000 0x1000>; interrupts = <0 113 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio6: gpio@b26000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb26000 0x1000>; interrupts = <0 114 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio7: gpio@b27000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb27000 0x1000>; interrupts = <0 115 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio8: gpio@b28000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb28000 0x1000>; interrupts = <0 116 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio9: gpio@b29000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb29000 0x1000>; interrupts = <0 117 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio10: gpio@b2a000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb2a000 0x1000>; interrupts = <0 118 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio11: gpio@b2b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb2b000 0x1000>; interrupts = <0 119 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio12: gpio@b2c000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb2c000 0x1000>; interrupts = <0 120 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio13: gpio@b2d000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb2d000 0x1000>; interrupts = <0 121 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio14: gpio@b2e000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb2e000 0x1000>; interrupts = <0 122 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio15: gpio@b2f000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb2f000 0x1000>; interrupts = <0 123 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio16: gpio@b30000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb30000 0x1000>; interrupts = <0 124 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio17: gpio@b31000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xb31000 0x1000>; interrupts = <0 125 0x4>; gpio-controller; #gpio-cells = <2>; clocks = <&clock HIX5HD2_FIXED_100M>; clock-names = "apb_pclk"; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; wdt0: watchdog@a2c000 { compatible = "arm,sp805", "arm,primecell"; arm,primecell-periphid = <0x00141805>; reg = <0xa2c000 0x1000>; interrupts = <0 29 4>; clocks = <&clock HIX5HD2_WDG0_RST>, <&clock HIX5HD2_WDG0_RST>; clock-names = "wdog_clk", "apb_pclk"; }; }; local_timer@a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; }; l2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x00a10000 0x100000>; interrupts = <0 15 4>; cache-unified; cache-level = <2>; }; sysctrl: system-controller@0 { compatible = "hisilicon,sysctrl", "syscon"; reg = <0x00000000 0x1000>; }; reboot { compatible = "syscon-reboot"; regmap = <&sysctrl>; offset = <0x4>; mask = <0xdeadbeef>; }; cpuctrl@a22000 { compatible = "hisilicon,cpuctrl"; #address-cells = <1>; #size-cells = <1>; reg = <0x00a22000 0x2000>; ranges = <0 0x00a22000 0x2000>; clock: clock@0 { compatible = "hisilicon,hix5hd2-clock"; reg = <0 0x2000>; #clock-cells = <1>; }; }; /* unremovable emmc as mmcblk0 */ mmc: mmc@1830000 { compatible = "snps,dw-mshc"; reg = <0x1830000 0x1000>; interrupts = <0 35 4>; clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>; clock-names = "biu", "ciu"; }; sd: mmc@1820000 { compatible = "snps,dw-mshc"; reg = <0x1820000 0x1000>; interrupts = <0 34 4>; clocks = <&clock HIX5HD2_SD_CIU_RST>, <&clock HIX5HD2_SD_BIU_CLK>; clock-names = "biu", "ciu"; }; gmac0: ethernet@1840000 { compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; reg = <0x1840000 0x1000>,<0x184300c 0x4>; interrupts = <0 71 4>; clocks = <&clock HIX5HD2_MAC0_CLK>; clock-names = "mac_core"; status = "disabled"; }; gmac1: ethernet@1841000 { compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; reg = <0x1841000 0x1000>,<0x1843010 0x4>; interrupts = <0 72 4>; clocks = <&clock HIX5HD2_MAC1_CLK>; clock-names = "mac_core"; status = "disabled"; }; usb0: usb@1890000 { compatible = "generic-ehci"; reg = <0x1890000 0x1000>; interrupts = <0 66 4>; clocks = <&clock HIX5HD2_USB_CLK>; }; usb1: usb@1880000 { compatible = "generic-ohci"; reg = <0x1880000 0x1000>; interrupts = <0 67 4>; clocks = <&clock HIX5HD2_USB_CLK>; }; peripheral_ctrl: syscon@a20000 { compatible = "hisilicon,peri-subctrl", "syscon"; reg = <0xa20000 0x1000>; }; sata_phy: phy@1900000 { compatible = "hisilicon,hix5hd2-sata-phy"; reg = <0x1900000 0x10000>; #phy-cells = <0>; hisilicon,peripheral-syscon = <&peripheral_ctrl>; hisilicon,power-reg = <0x8 10>; }; ahci: sata@1900000 { compatible = "hisilicon,hisi-ahci"; reg = <0x1900000 0x10000>; interrupts = <0 70 4>; clocks = <&clock HIX5HD2_SATA_CLK>; }; ir: ir@1000 { compatible = "hisilicon,hix5hd2-ir"; reg = <0x001000 0x1000>; interrupts = <0 47 4>; clocks = <&clock HIX5HD2_FIXED_24M>; hisilicon,power-syscon = <&sysctrl>; }; i2c0: i2c@b10000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0xb10000 0x1000>; interrupts = <0 38 4>; clocks = <&clock HIX5HD2_I2C0_RST>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@b11000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0xb11000 0x1000>; interrupts = <0 39 4>; clocks = <&clock HIX5HD2_I2C1_RST>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@b12000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0xb12000 0x1000>; interrupts = <0 40 4>; clocks = <&clock HIX5HD2_I2C2_RST>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@b13000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0xb13000 0x1000>; interrupts = <0 41 4>; clocks = <&clock HIX5HD2_I2C3_RST>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@b16000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0xb16000 0x1000>; interrupts = <0 43 4>; clocks = <&clock HIX5HD2_I2C4_RST>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c5: i2c@b17000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0xb17000 0x1000>; interrupts = <0 44 4>; clocks = <&clock HIX5HD2_I2C5_RST>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; }; |