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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 | /* Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DC_CLOCK_SOURCE_DCE_H__ #define __DC_CLOCK_SOURCE_DCE_H__ #include "../inc/clock_source.h" #define TO_DCE110_CLK_SRC(clk_src)\ container_of(clk_src, struct dce110_clk_src, base) #define CS_COMMON_REG_LIST_DCE_100_110(id) \ SRI(RESYNC_CNTL, PIXCLK, id), \ SRI(PLL_CNTL, BPHYC_PLL, id) #define CS_COMMON_REG_LIST_DCE_80(id) \ SRI(RESYNC_CNTL, PIXCLK, id), \ SRI(PLL_CNTL, DCCG_PLL, id) #define CS_COMMON_REG_LIST_DCE_112(id) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) #define CS_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(PHASE, DP_DTO, 2),\ SRII(PHASE, DP_DTO, 3),\ SRII(PHASE, DP_DTO, 4),\ SRII(PHASE, DP_DTO, 5),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 2),\ SRII(MODULO, DP_DTO, 3),\ SRII(MODULO, DP_DTO, 4),\ SRII(MODULO, DP_DTO, 5),\ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1),\ SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII(PIXEL_RATE_CNTL, OTG, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 4),\ SRII(PIXEL_RATE_CNTL, OTG, 5) #define CS_COMMON_REG_LIST_DCN201(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1) #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(PHASE, DP_DTO, 2),\ SRII(PHASE, DP_DTO, 3),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 2),\ SRII(MODULO, DP_DTO, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1),\ SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII(PIXEL_RATE_CNTL, OTG, 3) #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(PHASE, DP_DTO, 2),\ SRII(PHASE, DP_DTO, 3),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 2),\ SRII(MODULO, DP_DTO, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1),\ SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII(PIXEL_RATE_CNTL, OTG, 3) #define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(PHASE, DP_DTO, 2),\ SRII(PHASE, DP_DTO, 3),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 2),\ SRII(MODULO, DP_DTO, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1),\ SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII(PIXEL_RATE_CNTL, OTG, 3) #define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(PHASE, DP_DTO, 2),\ SRII(PHASE, DP_DTO, 3),\ SRII(PHASE, DP_DTO, 4),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 2),\ SRII(MODULO, DP_DTO, 3),\ SRII(MODULO, DP_DTO, 4),\ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1),\ SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII(PIXEL_RATE_CNTL, OTG, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 4) #define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1) #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) #define CS_COMMON_MASK_SH_LIST_DCN3_1_4(mask_sh)\ CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh), #define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\ CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh) #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ SRII(PHASE, DP_DTO, 1),\ SRII(PHASE, DP_DTO, 2),\ SRII(PHASE, DP_DTO, 3),\ SRII(MODULO, DP_DTO, 0),\ SRII(MODULO, DP_DTO, 1),\ SRII(MODULO, DP_DTO, 2),\ SRII(MODULO, DP_DTO, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 0), \ SRII(PIXEL_RATE_CNTL, OTG, 1), \ SRII(PIXEL_RATE_CNTL, OTG, 2), \ SRII(PIXEL_RATE_CNTL, OTG, 3) #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) #define CS_REG_FIELD_LIST(type) \ type PLL_REF_DIV_SRC; \ type DCCG_DEEP_COLOR_CNTL1; \ type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ type PLL_POST_DIV_PIXCLK; \ type PLL_REF_DIV; \ type DP_DTO0_PHASE; \ type DP_DTO0_MODULO; \ type DP_DTO0_ENABLE; #if defined(CONFIG_DRM_AMD_DC_DCN) #define CS_REG_FIELD_LIST_DCN32(type) \ type PIPE0_DTO_SRC_SEL; #endif struct dce110_clk_src_shift { CS_REG_FIELD_LIST(uint8_t) #if defined(CONFIG_DRM_AMD_DC_DCN) CS_REG_FIELD_LIST_DCN32(uint8_t) #endif }; struct dce110_clk_src_mask{ CS_REG_FIELD_LIST(uint32_t) #if defined(CONFIG_DRM_AMD_DC_DCN) CS_REG_FIELD_LIST_DCN32(uint32_t) #endif }; struct dce110_clk_src_regs { uint32_t RESYNC_CNTL; uint32_t PIXCLK_RESYNC_CNTL; uint32_t PLL_CNTL; /* below are for DTO. * todo: should probably use different struct to not waste space */ uint32_t PHASE[MAX_PIPES]; uint32_t MODULO[MAX_PIPES]; uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; }; struct dce110_clk_src { struct clock_source base; const struct dce110_clk_src_regs *regs; const struct dce110_clk_src_mask *cs_mask; const struct dce110_clk_src_shift *cs_shift; struct dc_bios *bios; struct spread_spectrum_data *dp_ss_params; uint32_t dp_ss_params_cnt; struct spread_spectrum_data *hdmi_ss_params; uint32_t hdmi_ss_params_cnt; struct spread_spectrum_data *dvi_ss_params; uint32_t dvi_ss_params_cnt; struct spread_spectrum_data *lvds_ss_params; uint32_t lvds_ss_params_cnt; uint32_t ext_clk_khz; uint32_t ref_freq_khz; struct calc_pll_clock_source calc_pll; struct calc_pll_clock_source calc_pll_hdmi; }; bool dce110_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id, const struct dce110_clk_src_regs *regs, const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_mask *cs_mask); bool dce112_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_mask *cs_mask); bool dcn20_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_mask *cs_mask); bool dcn3_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_mask *cs_mask); bool dcn301_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_mask *cs_mask); bool dcn31_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_mask *cs_mask); /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ struct pixel_rate_range_table_entry { unsigned int range_min_khz; unsigned int range_max_khz; unsigned int target_pixel_rate_khz; unsigned short mult_factor; unsigned short div_factor; }; extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[]; const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( unsigned int pixel_rate_khz); #endif |