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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Socionext UniPhier peripheral core reset in glue layer description: | Some peripheral core reset belongs to its own glue layer. Before using this core reset, it is necessary to control the clocks and resets to enable this layer. These clocks and resets should be described in each property. maintainers: - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> properties: compatible: enum: - socionext,uniphier-pro4-usb3-reset - socionext,uniphier-pro5-usb3-reset - socionext,uniphier-pxs2-usb3-reset - socionext,uniphier-ld20-usb3-reset - socionext,uniphier-pxs3-usb3-reset - socionext,uniphier-nx1-usb3-reset - socionext,uniphier-pro4-ahci-reset - socionext,uniphier-pxs2-ahci-reset - socionext,uniphier-pxs3-ahci-reset reg: maxItems: 1 "#reset-cells": const: 1 clocks: minItems: 1 maxItems: 2 clock-names: true resets: minItems: 1 maxItems: 2 reset-names: true allOf: - if: properties: compatible: contains: enum: - socionext,uniphier-pro4-usb3-reset - socionext,uniphier-pro5-usb3-reset - socionext,uniphier-pro4-ahci-reset then: properties: clocks: minItems: 2 maxItems: 2 clock-names: items: - const: gio - const: link resets: minItems: 2 maxItems: 2 reset-names: items: - const: gio - const: link else: properties: clocks: maxItems: 1 clock-names: const: link resets: maxItems: 1 reset-names: const: link additionalProperties: false required: - compatible - reg - "#reset-cells" - clocks - clock-names - resets - reset-names examples: - | usb_rst: reset-controller@0 { compatible = "socionext,uniphier-ld20-usb3-reset"; reg = <0x0 0x4>; #reset-cells = <1>; clock-names = "link"; clocks = <&sys_clk 14>; reset-names = "link"; resets = <&sys_rst 14>; }; |