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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC * * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries * * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> * */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mfd/atmel-flexcom.h> #include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/microchip,lan966x.h> / { model = "Microchip LAN966 family SoC"; compatible = "microchip,lan966"; interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; clock-frequency = <600000000>; reg = <0x0>; }; }; clocks { sys_clk: sys_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <165625000>; }; cpu_clk: cpu_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; ddr_clk: ddr_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; nic_clk: nic_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; clks: clock-controller@e00c00a8 { compatible = "microchip,lan966x-gck"; #clock-cells = <1>; clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; clock-names = "cpu", "ddr", "sys"; reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; }; timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <37500000>; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; udc: usb@200000 { compatible = "microchip,lan9662-udc", "atmel,sama5d3-udc"; reg = <0x00200000 0x80000>, <0xe0808000 0x400>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>; clock-names = "pclk", "hclk"; status = "disabled"; }; switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; reg = <0xe0000000 0x0100000>, <0xe2000000 0x0800000>; reg-names = "cpu", "gcb"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "xtr", "fdma", "ana", "ptp", "ptp-ext"; resets = <&reset 0>; reset-names = "switch"; status = "disabled"; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port0: port@0 { reg = <0>; status = "disabled"; }; port1: port@1 { reg = <1>; status = "disabled"; }; port2: port@2 { reg = <2>; status = "disabled"; }; port3: port@3 { reg = <3>; status = "disabled"; }; port4: port@4 { reg = <4>; status = "disabled"; }; port5: port@5 { reg = <5>; status = "disabled"; }; port6: port@6 { reg = <6>; status = "disabled"; }; port7: port@7 { reg = <7>; status = "disabled"; }; }; }; otp: otp@e0021000 { compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc"; reg = <0xe0021000 0x300>; }; flx0: flexcom@e0040000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0040000 0x100>; clocks = <&clks GCK_ID_FLEXCOM0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0040000 0x800>; status = "disabled"; usart0: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, <&dma0 AT91_XDMAC_DT_PERID(2)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi0: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, <&dma0 AT91_XDMAC_DT_PERID(2)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c0: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, <&dma0 AT91_XDMAC_DT_PERID(2)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; flx1: flexcom@e0044000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0044000 0x100>; clocks = <&clks GCK_ID_FLEXCOM1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0044000 0x800>; status = "disabled"; usart1: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, <&dma0 AT91_XDMAC_DT_PERID(4)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi1: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, <&dma0 AT91_XDMAC_DT_PERID(4)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, <&dma0 AT91_XDMAC_DT_PERID(4)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; trng: rng@e0048000 { compatible = "atmel,at91sam9g45-trng"; reg = <0xe0048000 0x100>; clocks = <&nic_clk>; }; aes: crypto@e004c000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xe004c000 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, <&dma0 AT91_XDMAC_DT_PERID(13)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "aes_clk"; }; flx2: flexcom@e0060000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0060000 0x100>; clocks = <&clks GCK_ID_FLEXCOM2>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0060000 0x800>; status = "disabled"; usart2: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, <&dma0 AT91_XDMAC_DT_PERID(6)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi2: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, <&dma0 AT91_XDMAC_DT_PERID(6)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, <&dma0 AT91_XDMAC_DT_PERID(6)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; flx3: flexcom@e0064000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0064000 0x100>; clocks = <&clks GCK_ID_FLEXCOM3>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0064000 0x800>; status = "disabled"; usart3: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, <&dma0 AT91_XDMAC_DT_PERID(8)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi3: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, <&dma0 AT91_XDMAC_DT_PERID(8)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, <&dma0 AT91_XDMAC_DT_PERID(8)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; dma0: dma-controller@e0068000 { compatible = "microchip,sama7g5-dma"; reg = <0xe0068000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; clocks = <&nic_clk>; clock-names = "dma_clk"; }; sha: crypto@e006c000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xe006c000 0xec>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; dma-names = "tx"; clocks = <&nic_clk>; clock-names = "sha_clk"; }; flx4: flexcom@e0070000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0070000 0x100>; clocks = <&clks GCK_ID_FLEXCOM4>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0070000 0x800>; status = "disabled"; usart4: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, <&dma0 AT91_XDMAC_DT_PERID(10)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi4: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, <&dma0 AT91_XDMAC_DT_PERID(10)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, <&dma0 AT91_XDMAC_DT_PERID(10)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; timer0: timer@e008c000 { compatible = "snps,dw-apb-timer"; reg = <0xe008c000 0x400>; clocks = <&nic_clk>; clock-names = "timer"; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; }; watchdog: watchdog@e0090000 { compatible = "snps,dw-wdt"; reg = <0xe0090000 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&nic_clk>; status = "disabled"; }; cpu_ctrl: syscon@e00c0000 { compatible = "microchip,lan966x-cpu-syscon", "syscon"; reg = <0xe00c0000 0x350>; }; can0: can@e081c000 { compatible = "bosch,m_can"; reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; reg-names = "m_can", "message_ram"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; clock-names = "hclk", "cclk"; assigned-clocks = <&clks GCK_ID_MCAN0>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; status = "disabled"; }; can1: can@e0820000 { compatible = "bosch,m_can"; reg = <0xe0820000 0xfc>, <0x00100000 0x8000>; reg-names = "m_can", "message_ram"; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>; clock-names = "hclk", "cclk"; assigned-clocks = <&clks GCK_ID_MCAN1>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>; status = "disabled"; }; reset: reset-controller@e200400c { compatible = "microchip,lan966x-switch-reset"; reg = <0xe200400c 0x4>; reg-names = "gcb"; #reset-cells = <1>; cpu-syscon = <&cpu_ctrl>; }; gpio: pinctrl@e2004064 { compatible = "microchip,lan966x-pinctrl"; reg = <0xe2004064 0xb4>, <0xe2010024 0x138>; resets = <&reset 0>; reset-names = "switch"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 78>; interrupt-controller; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; mdio0: mdio@e2004118 { compatible = "microchip,lan966x-miim"; #address-cells = <1>; #size-cells = <0>; reg = <0xe2004118 0x24>; clocks = <&sys_clk>; status = "disabled"; }; mdio1: mdio@e200413c { compatible = "microchip,lan966x-miim"; #address-cells = <1>; #size-cells = <0>; reg = <0xe200413c 0x24>, <0xe2010020 0x4>; clocks = <&sys_clk>; status = "disabled"; phy0: ethernet-phy@1 { reg = <1>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; phy1: ethernet-phy@2 { reg = <2>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; sgpio: gpio@e2004190 { compatible = "microchip,sparx5-sgpio"; reg = <0xe2004190 0x118>; clocks = <&sys_clk>; resets = <&reset 0>; reset-names = "switch"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; sgpio_in: gpio@0 { compatible = "microchip,sparx5-sgpio-bank"; reg = <0>; gpio-controller; #gpio-cells = <3>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>; }; sgpio_out: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; reg = <1>; gpio-controller; #gpio-cells = <3>; }; }; hwmon: hwmon@e2010180 { compatible = "microchip,lan9668-hwmon"; reg = <0xe2010180 0xc>, <0xe20042a8 0xc>; reg-names = "pvt", "fan"; clocks = <&sys_clk>; }; serdes: serdes@e202c000 { compatible = "microchip,lan966x-serdes"; reg = <0xe202c000 0x9c>, <0xe2004010 0x4>; #phy-cells = <2>; status = "disabled"; }; gic: interrupt-controller@e8c11000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; reg = <0xe8c11000 0x1000>, <0xe8c12000 0x2000>, <0xe8c14000 0x2000>, <0xe8c16000 0x2000>; }; }; }; |