// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

/dts-v1/;
#include <dt-bindings/pinctrl/mt65xx.h>

#include "mt7986a.dtsi"

/ {
	model = "MediaTek MT7986a RFB";
	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&crypto {
	status = "okay";
};

&eth {
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&mdio {
	switch: switch@0 {
		compatible = "mediatek,mt7531";
		reg = <31>;
		reset-gpios = <&pio 5 0>;
	};
};

&mmc0 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	bus-width = <8>;
	max-frequency = <200000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	hs400-ds-delay = <0x14014>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	non-removable;
	no-sd;
	no-sdio;
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_pins>;
	status = "okay";
};

&pcie_phy {
	status = "okay";
};

&pio {
	mmc0_pins_default: mmc0-pins {
		mux {
			function = "emmc";
			groups = "emmc_51";
		};
		conf-cmd-dat {
			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
			input-enable;
			drive-strength = <4>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
		};
		conf-clk {
			pins = "EMMC_CK";
			drive-strength = <6>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
		};
		conf-ds {
			pins = "EMMC_DSL";
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
		};
		conf-rst {
			pins = "EMMC_RSTB";
			drive-strength = <4>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
		};
	};

	mmc0_pins_uhs: mmc0-uhs-pins {
		mux {
			function = "emmc";
			groups = "emmc_51";
		};
		conf-cmd-dat {
			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
			input-enable;
			drive-strength = <4>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
		};
		conf-clk {
			pins = "EMMC_CK";
			drive-strength = <6>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
		};
		conf-ds {
			pins = "EMMC_DSL";
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
		};
		conf-rst {
			pins = "EMMC_RSTB";
			drive-strength = <4>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
		};
	};

	pcie_pins: pcie-pins {
		mux {
			function = "pcie";
			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
		};
	};

	spi_flash_pins: spi-flash-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};
	};

	spic_pins: spic-pins {
		mux {
			function = "spi";
			groups = "spi1_2";
		};
	};

	uart1_pins: uart1-pins {
		mux {
			function = "uart";
			groups = "uart1";
		};
	};

	uart2_pins: uart2-pins {
		mux {
			function = "uart";
			groups = "uart2";
		};
	};

	wf_2g_5g_pins: wf-2g-5g-pins {
		mux {
			function = "wifi";
			groups = "wf_2g", "wf_5g";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
			       "WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <4>;
		};
	};

	wf_dbdc_pins: wf-dbdc-pins {
		mux {
			function = "wifi";
			groups = "wf_dbdc";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA";
			drive-strength = <4>;
		};
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_flash_pins>;
	cs-gpios = <0>, <0>;
	status = "okay";
	spi_nand: spi_nand@0 {
		compatible = "spi-nand";
		reg = <0>;
		spi-max-frequency = <10000000>;
		spi-tx-buswidth = <4>;
		spi-rx-buswidth = <4>;
	};
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic_pins>;
	cs-gpios = <0>, <0>;
	status = "okay";
};

&ssusb {
	status = "okay";
};

&switch {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan0";
		};

		port@1 {
			reg = <1>;
			label = "lan1";
		};

		port@2 {
			reg = <2>;
			label = "lan2";
		};

		port@3 {
			reg = <3>;
			label = "lan3";
		};

		port@4 {
			reg = <4>;
			label = "lan4";
		};

		port@6 {
			reg = <6>;
			label = "cpu";
			ethernet = <&gmac0>;
			phy-mode = "2500base-x";

			fixed-link {
				speed = <2500>;
				full-duplex;
				pause;
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

&usb_phy {
	status = "okay";
};

&wifi {
	status = "okay";
	pinctrl-names = "default", "dbdc";
	pinctrl-0 = <&wf_2g_5g_pins>;
	pinctrl-1 = <&wf_dbdc_pins>;
};