[
    {
        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
        "EventCode": "0x84",
        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
        "CounterMask": "1",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
        "PerPkg": "1",
        "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
        "PerPkg": "1",
        "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
        "PerPkg": "1",
        "UMask": "0x20",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
        "EventCode": "0xff",
        "EventName": "UNC_CLOCK.SOCKET",
        "PerPkg": "1",
        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
        "Unit": "CLOCK"
    }
]