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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright 2014-2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef KFD_PM4_HEADERS_H_ #define KFD_PM4_HEADERS_H_ #ifndef PM4_MES_HEADER_DEFINED #define PM4_MES_HEADER_DEFINED union PM4_MES_TYPE_3_HEADER { struct { /* reserved */ uint32_t reserved1:8; /* IT opcode */ uint32_t opcode:8; /* number of DWORDs - 1 in the information body */ uint32_t count:14; /* packet identifier. It should be 3 for type 3 packets */ uint32_t type:2; }; uint32_t u32all; }; #endif /* PM4_MES_HEADER_DEFINED */ /*--------------------MES_MAP_PROCESS-------------------- */ #ifndef PM4_MES_MAP_PROCESS_DEFINED #define PM4_MES_MAP_PROCESS_DEFINED struct pm4_map_process { union { union PM4_MES_TYPE_3_HEADER header; /* header */ uint32_t ordinal1; }; union { struct { uint32_t pasid:16; uint32_t reserved1:8; uint32_t diq_enable:1; uint32_t process_quantum:7; } bitfields2; uint32_t ordinal2; }; union { struct { uint32_t page_table_base:28; uint32_t reserved3:4; } bitfields3; uint32_t ordinal3; }; uint32_t sh_mem_bases; uint32_t sh_mem_ape1_base; uint32_t sh_mem_ape1_limit; uint32_t sh_mem_config; uint32_t gds_addr_lo; uint32_t gds_addr_hi; union { struct { uint32_t num_gws:6; uint32_t reserved4:2; uint32_t num_oac:4; uint32_t reserved5:4; uint32_t gds_size:6; uint32_t num_queues:10; } bitfields10; uint32_t ordinal10; }; }; #endif #ifndef PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH #define PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH struct pm4_map_process_scratch_kv { union { union PM4_MES_TYPE_3_HEADER header; /* header */ uint32_t ordinal1; }; union { struct { uint32_t pasid:16; uint32_t reserved1:8; uint32_t diq_enable:1; uint32_t process_quantum:7; } bitfields2; uint32_t ordinal2; }; union { struct { uint32_t page_table_base:28; uint32_t reserved2:4; } bitfields3; uint32_t ordinal3; }; uint32_t reserved3; uint32_t sh_mem_bases; uint32_t sh_mem_config; uint32_t sh_mem_ape1_base; uint32_t sh_mem_ape1_limit; uint32_t sh_hidden_private_base_vmid; uint32_t reserved4; uint32_t reserved5; uint32_t gds_addr_lo; uint32_t gds_addr_hi; union { struct { uint32_t num_gws:6; uint32_t reserved6:2; uint32_t num_oac:4; uint32_t reserved7:4; uint32_t gds_size:6; uint32_t num_queues:10; } bitfields14; uint32_t ordinal14; }; uint32_t completion_signal_lo32; uint32_t completion_signal_hi32; }; #endif enum { CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 }; #endif /* KFD_PM4_HEADERS_H_ */ |