Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 | /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _N2_CORE_H #define _N2_CORE_H #ifndef __ASSEMBLY__ struct ino_blob { u64 intr; u64 ino; }; struct spu_mdesc_info { u64 cfg_handle; struct ino_blob *ino_table; int num_intrs; }; struct n2_crypto { struct spu_mdesc_info cwq_info; struct list_head cwq_list; }; struct n2_mau { struct spu_mdesc_info mau_info; struct list_head mau_list; }; #define CWQ_ENTRY_SIZE 64 #define CWQ_NUM_ENTRIES 64 #define MAU_ENTRY_SIZE 64 #define MAU_NUM_ENTRIES 64 struct cwq_initial_entry { u64 control; u64 src_addr; u64 auth_key_addr; u64 auth_iv_addr; u64 final_auth_state_addr; u64 enc_key_addr; u64 enc_iv_addr; u64 dest_addr; }; struct cwq_ext_entry { u64 len; u64 src_addr; u64 resv1; u64 resv2; u64 resv3; u64 resv4; u64 resv5; u64 resv6; }; struct cwq_final_entry { u64 control; u64 src_addr; u64 resv1; u64 resv2; u64 resv3; u64 resv4; u64 resv5; u64 resv6; }; #define CONTROL_LEN 0x000000000000ffffULL #define CONTROL_LEN_SHIFT 0 #define CONTROL_HMAC_KEY_LEN 0x0000000000ff0000ULL #define CONTROL_HMAC_KEY_LEN_SHIFT 16 #define CONTROL_ENC_TYPE 0x00000000ff000000ULL #define CONTROL_ENC_TYPE_SHIFT 24 #define ENC_TYPE_ALG_RC4_STREAM 0x00ULL #define ENC_TYPE_ALG_RC4_NOSTREAM 0x04ULL #define ENC_TYPE_ALG_DES 0x08ULL #define ENC_TYPE_ALG_3DES 0x0cULL #define ENC_TYPE_ALG_AES128 0x10ULL #define ENC_TYPE_ALG_AES192 0x14ULL #define ENC_TYPE_ALG_AES256 0x18ULL #define ENC_TYPE_ALG_RESERVED 0x1cULL #define ENC_TYPE_ALG_MASK 0x1cULL #define ENC_TYPE_CHAINING_ECB 0x00ULL #define ENC_TYPE_CHAINING_CBC 0x01ULL #define ENC_TYPE_CHAINING_CFB 0x02ULL #define ENC_TYPE_CHAINING_COUNTER 0x03ULL #define ENC_TYPE_CHAINING_MASK 0x03ULL #define CONTROL_AUTH_TYPE 0x0000001f00000000ULL #define CONTROL_AUTH_TYPE_SHIFT 32 #define AUTH_TYPE_RESERVED 0x00ULL #define AUTH_TYPE_MD5 0x01ULL #define AUTH_TYPE_SHA1 0x02ULL #define AUTH_TYPE_SHA256 0x03ULL #define AUTH_TYPE_CRC32 0x04ULL #define AUTH_TYPE_HMAC_MD5 0x05ULL #define AUTH_TYPE_HMAC_SHA1 0x06ULL #define AUTH_TYPE_HMAC_SHA256 0x07ULL #define AUTH_TYPE_TCP_CHECKSUM 0x08ULL #define AUTH_TYPE_SSL_HMAC_MD5 0x09ULL #define AUTH_TYPE_SSL_HMAC_SHA1 0x0aULL #define AUTH_TYPE_SSL_HMAC_SHA256 0x0bULL #define CONTROL_STRAND 0x000000e000000000ULL #define CONTROL_STRAND_SHIFT 37 #define CONTROL_HASH_LEN 0x0000ff0000000000ULL #define CONTROL_HASH_LEN_SHIFT 40 #define CONTROL_INTERRUPT 0x0001000000000000ULL #define CONTROL_STORE_FINAL_AUTH_STATE 0x0002000000000000ULL #define CONTROL_RESERVED 0x001c000000000000ULL #define CONTROL_HV_DONE 0x0004000000000000ULL #define CONTROL_HV_PROTOCOL_ERROR 0x0008000000000000ULL #define CONTROL_HV_HARDWARE_ERROR 0x0010000000000000ULL #define CONTROL_END_OF_BLOCK 0x0020000000000000ULL #define CONTROL_START_OF_BLOCK 0x0040000000000000ULL #define CONTROL_ENCRYPT 0x0080000000000000ULL #define CONTROL_OPCODE 0xff00000000000000ULL #define CONTROL_OPCODE_SHIFT 56 #define OPCODE_INPLACE_BIT 0x80ULL #define OPCODE_SSL_KEYBLOCK 0x10ULL #define OPCODE_COPY 0x20ULL #define OPCODE_ENCRYPT 0x40ULL #define OPCODE_AUTH_MAC 0x41ULL #endif /* !(__ASSEMBLY__) */ /* NCS v2.0 hypervisor interfaces */ #define HV_NCS_QTYPE_MAU 0x01 #define HV_NCS_QTYPE_CWQ 0x02 /* ncs_qconf() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_NCS_QCONF * ARG0: Queue type (HV_NCS_QTYPE_{MAU,CWQ}) * ARG1: Real address of queue, or handle for unconfigure * ARG2: Number of entries in queue, zero for unconfigure * RET0: status * RET1: queue handle * * Configure a queue in the stream processing unit. * * The real address given as the base must be 64-byte * aligned. * * The queue size can range from a minimum of 2 to a maximum * of 64. The queue size must be a power of two. * * To unconfigure a queue, specify a length of zero and place * the queue handle into ARG1. * * On configure success the hypervisor will set the FIRST, HEAD, * and TAIL registers to the address of the first entry in the * queue. The LAST register will be set to point to the last * entry in the queue. */ #define HV_FAST_NCS_QCONF 0x111 /* ncs_qinfo() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_NCS_QINFO * ARG0: Queue handle * RET0: status * RET1: Queue type (HV_NCS_QTYPE_{MAU,CWQ}) * RET2: Queue base address * RET3: Number of entries */ #define HV_FAST_NCS_QINFO 0x112 /* ncs_gethead() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_NCS_GETHEAD * ARG0: Queue handle * RET0: status * RET1: queue head offset */ #define HV_FAST_NCS_GETHEAD 0x113 /* ncs_gettail() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_NCS_GETTAIL * ARG0: Queue handle * RET0: status * RET1: queue tail offset */ #define HV_FAST_NCS_GETTAIL 0x114 /* ncs_settail() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_NCS_SETTAIL * ARG0: Queue handle * ARG1: New tail offset * RET0: status */ #define HV_FAST_NCS_SETTAIL 0x115 /* ncs_qhandle_to_devino() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_NCS_QHANDLE_TO_DEVINO * ARG0: Queue handle * RET0: status * RET1: devino */ #define HV_FAST_NCS_QHANDLE_TO_DEVINO 0x116 /* ncs_sethead_marker() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_NCS_SETHEAD_MARKER * ARG0: Queue handle * ARG1: New head offset * RET0: status */ #define HV_FAST_NCS_SETHEAD_MARKER 0x117 #ifndef __ASSEMBLY__ extern unsigned long sun4v_ncs_qconf(unsigned long queue_type, unsigned long queue_ra, unsigned long num_entries, unsigned long *qhandle); extern unsigned long sun4v_ncs_qinfo(unsigned long qhandle, unsigned long *queue_type, unsigned long *queue_ra, unsigned long *num_entries); extern unsigned long sun4v_ncs_gethead(unsigned long qhandle, unsigned long *head); extern unsigned long sun4v_ncs_gettail(unsigned long qhandle, unsigned long *tail); extern unsigned long sun4v_ncs_settail(unsigned long qhandle, unsigned long tail); extern unsigned long sun4v_ncs_qhandle_to_devino(unsigned long qhandle, unsigned long *devino); extern unsigned long sun4v_ncs_sethead_marker(unsigned long qhandle, unsigned long head); #endif /* !(__ASSEMBLY__) */ #endif /* _N2_CORE_H */ |