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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 | # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Multimedia Clock & Reset Controller maintainers: - Jeffrey Hugo <quic_jhugo@quicinc.com> - Taniya Das <tdas@codeaurora.org> description: | Qualcomm multimedia clock control module provides the clocks, resets and power domains. properties: compatible: enum: - qcom,mmcc-apq8064 - qcom,mmcc-apq8084 - qcom,mmcc-msm8226 - qcom,mmcc-msm8660 - qcom,mmcc-msm8960 - qcom,mmcc-msm8974 - qcom,mmcc-msm8992 - qcom,mmcc-msm8994 - qcom,mmcc-msm8996 - qcom,mmcc-msm8998 - qcom,mmcc-sdm630 - qcom,mmcc-sdm660 clocks: minItems: 8 maxItems: 10 clock-names: minItems: 8 maxItems: 10 '#clock-cells': const: 1 '#reset-cells': const: 1 '#power-domain-cells': const: 1 reg: maxItems: 1 protected-clocks: description: Protected clock specifier list as per common clock binding vdd-gfx-supply: description: Regulator supply for the GPU_GX GDSC required: - compatible - reg - '#clock-cells' - '#reset-cells' - '#power-domain-cells' additionalProperties: false allOf: - if: properties: compatible: contains: enum: - qcom,mmcc-apq8064 - qcom,mmcc-msm8960 then: properties: clocks: items: - description: Board PXO source - description: PLL 3 clock - description: PLL 3 Vote clock - description: DSI phy instance 1 dsi clock - description: DSI phy instance 1 byte clock - description: DSI phy instance 2 dsi clock - description: DSI phy instance 2 byte clock - description: HDMI phy PLL clock clock-names: items: - const: pxo - const: pll3 - const: pll8_vote - const: dsi1pll - const: dsi1pllbyte - const: dsi2pll - const: dsi2pllbyte - const: hdmipll - if: properties: compatible: contains: enum: - qcom,mmcc-msm8974 then: properties: clocks: items: - description: Board XO source - description: MMSS GPLL0 voted clock - description: GPLL0 voted clock - description: GPLL1 voted clock - description: GFX3D clock source - description: DSI phy instance 0 dsi clock - description: DSI phy instance 0 byte clock - description: DSI phy instance 1 dsi clock - description: DSI phy instance 1 byte clock - description: HDMI phy PLL clock - description: eDP phy PLL link clock - description: eDP phy PLL vco clock clock-names: items: - const: xo - const: mmss_gpll0_vote - const: gpll0_vote - const: gpll1_vote - const: gfx3d_clk_src - const: dsi0pll - const: dsi0pllbyte - const: dsi1pll - const: dsi1pllbyte - const: hdmipll - const: edp_link_clk - const: edp_vco_div - if: properties: compatible: contains: enum: - qcom,mmcc-msm8994 - qcom,mmcc-msm8998 - qcom,mmcc-sdm630 - qcom,mmcc-sdm660 then: required: - clocks - clock-names - if: properties: compatible: contains: const: qcom,mmcc-msm8994 then: properties: clocks: items: - description: Board XO source - description: Global PLL 0 clock - description: MMSS NoC AHB clock - description: GFX3D clock - description: DSI phy instance 0 dsi clock - description: DSI phy instance 0 byte clock - description: DSI phy instance 1 dsi clock - description: DSI phy instance 1 byte clock - description: HDMI phy PLL clock clock-names: items: - const: xo - const: gpll0 - const: mmssnoc_ahb - const: oxili_gfx3d_clk_src - const: dsi0pll - const: dsi0pllbyte - const: dsi1pll - const: dsi1pllbyte - const: hdmipll - if: properties: compatible: contains: const: qcom,mmcc-msm8996 then: properties: clocks: items: - description: Board XO source - description: Global PLL 0 clock - description: MMSS NoC AHB clock - description: DSI phy instance 0 dsi clock - description: DSI phy instance 0 byte clock - description: DSI phy instance 1 dsi clock - description: DSI phy instance 1 byte clock - description: HDMI phy PLL clock clock-names: items: - const: xo - const: gpll0 - const: gcc_mmss_noc_cfg_ahb_clk - const: dsi0pll - const: dsi0pllbyte - const: dsi1pll - const: dsi1pllbyte - const: hdmipll - if: properties: compatible: contains: const: qcom,mmcc-msm8998 then: properties: clocks: items: - description: Board XO source - description: Global PLL 0 clock - description: DSI phy instance 0 dsi clock - description: DSI phy instance 0 byte clock - description: DSI phy instance 1 dsi clock - description: DSI phy instance 1 byte clock - description: HDMI phy PLL clock - description: DisplayPort phy PLL link clock - description: DisplayPort phy PLL vco clock - description: Test clock clock-names: items: - const: xo - const: gpll0 - const: dsi0dsi - const: dsi0byte - const: dsi1dsi - const: dsi1byte - const: hdmipll - const: dplink - const: dpvco - const: core_bi_pll_test_se - if: properties: compatible: contains: enum: - qcom,mmcc-sdm630 - qcom,mmcc-sdm660 then: properties: clocks: items: - description: Board XO source - description: Board sleep source - description: Global PLL 0 clock - description: Global PLL 0 DIV clock - description: DSI phy instance 0 dsi clock - description: DSI phy instance 0 byte clock - description: DSI phy instance 1 dsi clock - description: DSI phy instance 1 byte clock - description: DisplayPort phy PLL link clock - description: DisplayPort phy PLL vco clock clock-names: items: - const: xo - const: sleep_clk - const: gpll0 - const: gpll0_div - const: dsi0pll - const: dsi0pllbyte - const: dsi1pll - const: dsi1pllbyte - const: dp_link_2x_clk_divsel_five - const: dp_vco_divided_clk_src_mux examples: # Example for MMCC for MSM8960: - | clock-controller@4000000 { compatible = "qcom,mmcc-msm8960"; reg = <0x4000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; ... |