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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2017-2020 NXP * Dong Aisheng <aisheng.dong@nxp.com> */ #include <dt-bindings/clock/imx8-clock.h> #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/pads-imx8qxp.h> #include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { ethernet0 = &fec1; ethernet1 = &fec2; gpio0 = &lsio_gpio0; gpio1 = &lsio_gpio1; gpio2 = &lsio_gpio2; gpio3 = &lsio_gpio3; gpio4 = &lsio_gpio4; gpio5 = &lsio_gpio5; gpio6 = &lsio_gpio6; gpio7 = &lsio_gpio7; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; mu0 = &lsio_mu0; mu1 = &lsio_mu1; mu2 = &lsio_mu2; mu3 = &lsio_mu3; mu4 = &lsio_mu4; serial0 = &lpuart0; serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; vpu_core0 = &vpu_core0; vpu_core1 = &vpu_core1; vpu_core2 = &vpu_core2; }; cpus { #address-cells = <2>; #size-cells = <0>; /* We have 1 clusters with 4 Cortex-A35 cores */ A35_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; A35_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; A35_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; A35_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; A35_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <1024>; }; }; a35_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <1000000>; clock-latency-ns = <150000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1100000>; clock-latency-ns = <150000>; opp-suspend; }; }; gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; decoder_boot: decoder-boot@84000000 { reg = <0 0x84000000 0 0x2000000>; no-map; }; encoder_boot: encoder-boot@86000000 { reg = <0 0x86000000 0 0x200000>; no-map; }; decoder_rpc: decoder-rpc@92000000 { reg = <0 0x92000000 0 0x100000>; no-map; }; dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; encoder_rpc: encoder-rpc@94400000 { reg = <0 0x94400000 0 0x700000>; no-map; }; }; pmu { compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", "rx0", "gip3"; mboxes = <&lsio_mu1 0 0 &lsio_mu1 1 0 &lsio_mu1 3 3>; pd: power-controller { compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; clk: clock-controller { compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; #clock-cells = <2>; }; iomuxc: pinctrl { compatible = "fsl,imx8qxp-iomuxc"; }; ocotp: ocotp { compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; }; scu_key: keys { compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; linux,keycodes = <KEY_POWER>; status = "disabled"; }; rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; watchdog { compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; timeout-sec = <60>; }; tsens: thermal-sensor { compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; #thermal-sensor-cells = <1>; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "xtal_32KHz"; }; xtal24m: clock-xtal24m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "xtal_24MHz"; }; thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; trips { cpu_alert0: trip0 { temperature = <107000>; hysteresis = <2000>; type = "passive"; }; cpu_crit0: trip1 { temperature = <127000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_alert0>; cooling-device = <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" }; #include "imx8qxp-ss-img.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi" |