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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * * Copyright (C) 2012 Marvell * * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * * Contains definitions specific to the Armada XP MV78260 SoC that are not * common to all Armada XP SoCs. */ #include "armada-xp.dtsi" / { model = "Marvell Armada XP MV78260 SoC"; compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; aliases { gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; }; cpus { #address-cells = <1>; #size-cells = <0>; enable-method = "marvell,armada-xp-smp"; cpu@0 { device_type = "cpu"; compatible = "marvell,sheeva-v7"; reg = <0>; clocks = <&cpuclk 0>; clock-latency = <1000000>; }; cpu@1 { device_type = "cpu"; compatible = "marvell,sheeva-v7"; reg = <1>; clocks = <&cpuclk 1>; clock-latency = <1000000>; }; }; soc { /* * MV78260 has 3 PCIe units Gen2.0: Two units can be * configured as x4 or quad x1 lanes. One unit is * x4 only. */ pciec: pcie@82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 0>, <0 0 0 2 &pcie1_intc 1>, <0 0 0 3 &pcie1_intc 2>, <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; pcie1_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 59>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie2_intc 0>, <0 0 0 2 &pcie2_intc 1>, <0 0 0 3 &pcie2_intc 2>, <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; pcie2_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 60>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie3_intc 0>, <0 0 0 2 &pcie3_intc 1>, <0 0 0 3 &pcie3_intc 2>, <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; clocks = <&gateclk 7>; status = "disabled"; pcie3_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 61>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie4_intc 0>, <0 0 0 2 &pcie4_intc 1>, <0 0 0 3 &pcie4_intc 2>, <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; clocks = <&gateclk 8>; status = "disabled"; pcie4_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie5: pcie@5,0 { device_type = "pci"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie5_intc 0>, <0 0 0 2 &pcie5_intc 1>, <0 0 0 3 &pcie5_intc 2>, <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; pcie5_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie6: pcie@6,0 { device_type = "pci"; assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; reg = <0x3000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 63>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie6_intc 0>, <0 0 0 2 &pcie6_intc 1>, <0 0 0 3 &pcie6_intc 2>, <0 0 0 4 &pcie6_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; clocks = <&gateclk 10>; status = "disabled"; pcie6_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie7: pcie@7,0 { device_type = "pci"; assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; reg = <0x3800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 64>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie7_intc 0>, <0 0 0 2 &pcie7_intc 1>, <0 0 0 3 &pcie7_intc 2>, <0 0 0 4 &pcie7_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; clocks = <&gateclk 11>; status = "disabled"; pcie7_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie8: pcie@8,0 { device_type = "pci"; assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; reg = <0x4000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 65>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie8_intc 0>, <0 0 0 2 &pcie8_intc 1>, <0 0 0 3 &pcie8_intc 2>, <0 0 0 4 &pcie8_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; clocks = <&gateclk 12>; status = "disabled"; pcie8_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; pcie9: pcie@9,0 { device_type = "pci"; assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; interrupt-names = "intx"; interrupts-extended = <&mpic 99>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie9_intc 0>, <0 0 0 2 &pcie9_intc 1>, <0 0 0 3 &pcie9_intc 2>, <0 0 0 4 &pcie9_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 26>; status = "disabled"; pcie9_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; }; }; }; internal-regs { gpio0: gpio@18100 { compatible = "marvell,armada-370-gpio", "marvell,orion-gpio"; reg = <0x18100 0x40>, <0x181c0 0x08>; reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; clocks = <&coreclk 0>; }; gpio1: gpio@18140 { compatible = "marvell,armada-370-gpio", "marvell,orion-gpio"; reg = <0x18140 0x40>, <0x181c8 0x08>; reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; clocks = <&coreclk 0>; }; gpio2: gpio@18180 { compatible = "marvell,armada-370-gpio", "marvell,orion-gpio"; reg = <0x18180 0x40>; ngpios = <3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <91>; }; eth3: ethernet@34000 { compatible = "marvell,armada-xp-neta"; reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; }; }; }; }; &pinctrl { compatible = "marvell,mv78260-pinctrl"; }; |