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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 | // SPDX-License-Identifier: GPL-2.0 /* * ARM Ltd. Fast Models * * Architecture Envelope Model (AEM) ARMv8-A * ARMAEMv8AMPCT * * RTSM_VE_AEMv8A.lisa */ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> /memreserve/ 0x80000000 0x00010000; #include "rtsm_ve-motherboard.dtsi" / { model = "RTSM_VE_AEMv8A"; compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { serial0 = &v2m_serial0; serial1 = &v2m_serial1; serial2 = &v2m_serial2; serial3 = &v2m_serial3; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; }; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x80000000>, <0x00000008 0x80000000 0 0x80000000>; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* Chipselect 2,00000000 is physically at 0x18000000 */ vram: vram@18000000 { /* 8 MB of designated video RAM */ compatible = "shared-dma-pool"; reg = <0x00000000 0x18000000 0 0x00800000>; no-map; }; }; gic: interrupt-controller@2c001000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0x2c001000 0 0x1000>, <0x0 0x2c002000 0 0x2000>, <0x0 0x2c004000 0 0x2000>, <0x0 0x2c006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <100000000>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; }; panel { compatible = "arm,rtsm-display"; port { panel_in: endpoint { remote-endpoint = <&clcd_pads>; }; }; }; bus@8000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; }; }; |