// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright (C) 2020 PHYTEC Messtechnik GmbH
// Author: Jens Lang <J.Lang@phytec.de>
// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx7d.dtsi"
/ {
model = "Storopack SMEGW01 board";
compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;
mmc0 = &usdhc1;
mmc1 = &usdhc3;
mmc2 = &usdhc2;
rtc0 = &i2c_rtc;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reg_lte_on: regulator-lte-on {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lte_on>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "lte_on";
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_lte_nreset: regulator-lte-nreset {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lte_nreset>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "LTE_nReset";
gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_wifi: regulator-wifi {
compatible = "regulator-fixed";
gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
regulator-name = "wifi_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_wlan_rfkill: regulator-wlan-rfkill {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rfkill>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "wlan_rfkill";
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usbotg_vbus: regulator-usbotg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay";
sram@0 {
compatible = "microchip,48l640";
reg = <0>;
spi-max-frequency = <16000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
fsl,magic-packet;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
ethphy1: ethernet-phy@2 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
reg = <2>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii-id";
phy-handle = <ðphy1>;
fsl,magic-packet;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
i2c_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_int>;
reg = <0x52>;
interrupt-parent = <&gpio2>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
dr_mode = "otg";
vbus-supply = <®_usbotg_vbus>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
over-current-active-low;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
wakeup-source;
keep-power-in-suspend;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
vmmc-supply = <®_wifi>;
wakeup-source;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
max-frequency = <200000000>;
bus-width = <8>;
fsl,tuning-step = <1>;
non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
>;
};
pinctrl_lte_on: lteongrp {
fsl,pins = <
MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
>;
};
pinctrl_lte_nreset: ltenresetgrp {
fsl,pins = <
MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
>;
};
pinctrl_rfkill: rfkillgrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
>;
};
pinctrl_usbotg1_lpsr: usbotg1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
>;
};
pinctrl_usbotg1_pwr: usbotg1-pwrgrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
>;
};
pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpiogrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
>;
};
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x5c
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
>;
};
};
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};
