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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Marvell 88E6xxx VLAN [Spanning Tree] Translation Unit (VTU [STU]) support * * Copyright (c) 2008 Marvell Semiconductor * Copyright (c) 2015 CMC Electronics, Inc. * Copyright (c) 2017 Savoir-faire Linux, Inc. */ #include <linux/bitfield.h> #include <linux/interrupt.h> #include <linux/irqdomain.h> #include "chip.h" #include "global1.h" #include "trace.h" /* Offset 0x02: VTU FID Register */ static int mv88e6xxx_g1_vtu_fid_read(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { u16 val; int err; err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_FID, &val); if (err) return err; entry->fid = val & MV88E6352_G1_VTU_FID_MASK; entry->policy = !!(val & MV88E6352_G1_VTU_FID_VID_POLICY); return 0; } static int mv88e6xxx_g1_vtu_fid_write(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { u16 val = entry->fid & MV88E6352_G1_VTU_FID_MASK; if (entry->policy) val |= MV88E6352_G1_VTU_FID_VID_POLICY; return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_FID, val); } /* Offset 0x03: VTU SID Register */ static int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip, u8 *sid) { u16 val; int err; err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_SID, &val); if (err) return err; *sid = val & MV88E6352_G1_VTU_SID_MASK; return 0; } static int mv88e6xxx_g1_vtu_sid_write(struct mv88e6xxx_chip *chip, u8 sid) { u16 val = sid & MV88E6352_G1_VTU_SID_MASK; return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_SID, val); } /* Offset 0x05: VTU Operation Register */ static int mv88e6xxx_g1_vtu_op_wait(struct mv88e6xxx_chip *chip) { int bit = __bf_shf(MV88E6XXX_G1_VTU_OP_BUSY); return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_VTU_OP, bit, 0); } static int mv88e6xxx_g1_vtu_op(struct mv88e6xxx_chip *chip, u16 op) { int err; err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_OP, MV88E6XXX_G1_VTU_OP_BUSY | op); if (err) return err; return mv88e6xxx_g1_vtu_op_wait(chip); } /* Offset 0x06: VTU VID Register */ static int mv88e6xxx_g1_vtu_vid_read(struct mv88e6xxx_chip *chip, bool *valid, u16 *vid) { u16 val; int err; err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_VID, &val); if (err) return err; if (vid) { *vid = val & 0xfff; if (val & MV88E6390_G1_VTU_VID_PAGE) *vid |= 0x1000; } if (valid) *valid = !!(val & MV88E6XXX_G1_VTU_VID_VALID); return 0; } static int mv88e6xxx_g1_vtu_vid_write(struct mv88e6xxx_chip *chip, bool valid, u16 vid) { u16 val = vid & 0xfff; if (vid & 0x1000) val |= MV88E6390_G1_VTU_VID_PAGE; if (valid) val |= MV88E6XXX_G1_VTU_VID_VALID; return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_VID, val); } /* Offset 0x07: VTU/STU Data Register 1 * Offset 0x08: VTU/STU Data Register 2 * Offset 0x09: VTU/STU Data Register 3 */ static int mv88e6185_g1_vtu_stu_data_read(struct mv88e6xxx_chip *chip, u16 *regs) { int i; /* Read all 3 VTU/STU Data registers */ for (i = 0; i < 3; ++i) { u16 *reg = ®s[i]; int err; err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); if (err) return err; } return 0; } static int mv88e6185_g1_vtu_data_read(struct mv88e6xxx_chip *chip, u8 *member, u8 *state) { u16 regs[3]; int err; int i; err = mv88e6185_g1_vtu_stu_data_read(chip, regs); if (err) return err; /* Extract MemberTag data */ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { unsigned int member_offset = (i % 4) * 4; unsigned int state_offset = member_offset + 2; if (member) member[i] = (regs[i / 4] >> member_offset) & 0x3; if (state) state[i] = (regs[i / 4] >> state_offset) & 0x3; } return 0; } static int mv88e6185_g1_vtu_data_write(struct mv88e6xxx_chip *chip, u8 *member, u8 *state) { u16 regs[3] = { 0 }; int i; /* Insert MemberTag and PortState data */ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { unsigned int member_offset = (i % 4) * 4; unsigned int state_offset = member_offset + 2; if (member) regs[i / 4] |= (member[i] & 0x3) << member_offset; if (state) regs[i / 4] |= (state[i] & 0x3) << state_offset; } /* Write all 3 VTU/STU Data registers */ for (i = 0; i < 3; ++i) { u16 reg = regs[i]; int err; err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); if (err) return err; } return 0; } static int mv88e6390_g1_vtu_data_read(struct mv88e6xxx_chip *chip, u8 *data) { u16 regs[2]; int i; /* Read the 2 VTU/STU Data registers */ for (i = 0; i < 2; ++i) { u16 *reg = ®s[i]; int err; err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); if (err) return err; } /* Extract data */ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { unsigned int offset = (i % 8) * 2; data[i] = (regs[i / 8] >> offset) & 0x3; } return 0; } static int mv88e6390_g1_vtu_data_write(struct mv88e6xxx_chip *chip, u8 *data) { u16 regs[2] = { 0 }; int i; /* Insert data */ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { unsigned int offset = (i % 8) * 2; regs[i / 8] |= (data[i] & 0x3) << offset; } /* Write the 2 VTU/STU Data registers */ for (i = 0; i < 2; ++i) { u16 reg = regs[i]; int err; err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); if (err) return err; } return 0; } /* VLAN Translation Unit Operations */ int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; /* To get the next higher active VID, the VTU GetNext operation can be * started again without setting the VID registers since it already * contains the last VID. * * To save a few hardware accesses and abstract this to the caller, * write the VID only once, when the entry is given as invalid. */ if (!entry->valid) { err = mv88e6xxx_g1_vtu_vid_write(chip, false, entry->vid); if (err) return err; } err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT); if (err) return err; return mv88e6xxx_g1_vtu_vid_read(chip, &entry->valid, &entry->vid); } int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { u16 val; int err; err = mv88e6xxx_g1_vtu_getnext(chip, entry); if (err) return err; if (entry->valid) { err = mv88e6185_g1_vtu_data_read(chip, entry->member, entry->state); if (err) return err; /* VTU DBNum[3:0] are located in VTU Operation 3:0 * VTU DBNum[7:4] ([5:4] for 6250) are located in VTU Operation 11:8 (9:8) */ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val); if (err) return err; entry->fid = val & 0x000f; entry->fid |= (val & 0x0f00) >> 4; entry->fid &= mv88e6xxx_num_databases(chip) - 1; } return 0; } int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { int err; /* Fetch VLAN MemberTag data from the VTU */ err = mv88e6xxx_g1_vtu_getnext(chip, entry); if (err) return err; if (entry->valid) { err = mv88e6185_g1_vtu_data_read(chip, entry->member, NULL); if (err) return err; err = mv88e6xxx_g1_vtu_fid_read(chip, entry); if (err) return err; err = mv88e6xxx_g1_vtu_sid_read(chip, &entry->sid); if (err) return err; } return 0; } int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { int err; /* Fetch VLAN MemberTag data from the VTU */ err = mv88e6xxx_g1_vtu_getnext(chip, entry); if (err) return err; if (entry->valid) { err = mv88e6390_g1_vtu_data_read(chip, entry->member); if (err) return err; err = mv88e6xxx_g1_vtu_fid_read(chip, entry); if (err) return err; err = mv88e6xxx_g1_vtu_sid_read(chip, &entry->sid); if (err) return err; } return 0; } int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { u16 op = MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE; int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; err = mv88e6xxx_g1_vtu_vid_write(chip, entry->valid, entry->vid); if (err) return err; if (entry->valid) { err = mv88e6185_g1_vtu_data_write(chip, entry->member, entry->state); if (err) return err; /* VTU DBNum[3:0] are located in VTU Operation 3:0 * VTU DBNum[7:4] are located in VTU Operation 11:8 * * For the 6250/6220, the latter are really [5:4] and * 9:8, but in those cases bits 7:6 of entry->fid are * 0 since they have num_databases = 64. */ op |= entry->fid & 0x000f; op |= (entry->fid & 0x00f0) << 4; } return mv88e6xxx_g1_vtu_op(chip, op); } int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; err = mv88e6xxx_g1_vtu_vid_write(chip, entry->valid, entry->vid); if (err) return err; if (entry->valid) { /* Write MemberTag data */ err = mv88e6185_g1_vtu_data_write(chip, entry->member, NULL); if (err) return err; err = mv88e6xxx_g1_vtu_fid_write(chip, entry); if (err) return err; err = mv88e6xxx_g1_vtu_sid_write(chip, entry->sid); if (err) return err; } /* Load/Purge VTU entry */ return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE); } int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry) { int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; err = mv88e6xxx_g1_vtu_vid_write(chip, entry->valid, entry->vid); if (err) return err; if (entry->valid) { /* Write MemberTag data */ err = mv88e6390_g1_vtu_data_write(chip, entry->member); if (err) return err; err = mv88e6xxx_g1_vtu_fid_write(chip, entry); if (err) return err; err = mv88e6xxx_g1_vtu_sid_write(chip, entry->sid); if (err) return err; } /* Load/Purge VTU entry */ return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE); } int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip) { int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_FLUSH_ALL); } /* Spanning Tree Unit Operations */ int mv88e6xxx_g1_stu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry) { int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; /* To get the next higher active SID, the STU GetNext operation can be * started again without setting the SID registers since it already * contains the last SID. * * To save a few hardware accesses and abstract this to the caller, * write the SID only once, when the entry is given as invalid. */ if (!entry->valid) { err = mv88e6xxx_g1_vtu_sid_write(chip, entry->sid); if (err) return err; } err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_STU_GET_NEXT); if (err) return err; err = mv88e6xxx_g1_vtu_vid_read(chip, &entry->valid, NULL); if (err) return err; if (entry->valid) { err = mv88e6xxx_g1_vtu_sid_read(chip, &entry->sid); if (err) return err; } return 0; } int mv88e6352_g1_stu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry) { int err; err = mv88e6xxx_g1_stu_getnext(chip, entry); if (err) return err; if (!entry->valid) return 0; return mv88e6185_g1_vtu_data_read(chip, NULL, entry->state); } int mv88e6390_g1_stu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry) { int err; err = mv88e6xxx_g1_stu_getnext(chip, entry); if (err) return err; if (!entry->valid) return 0; return mv88e6390_g1_vtu_data_read(chip, entry->state); } int mv88e6352_g1_stu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry) { int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; err = mv88e6xxx_g1_vtu_vid_write(chip, entry->valid, 0); if (err) return err; err = mv88e6xxx_g1_vtu_sid_write(chip, entry->sid); if (err) return err; if (entry->valid) { err = mv88e6185_g1_vtu_data_write(chip, NULL, entry->state); if (err) return err; } /* Load/Purge STU entry */ return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE); } int mv88e6390_g1_stu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry) { int err; err = mv88e6xxx_g1_vtu_op_wait(chip); if (err) return err; err = mv88e6xxx_g1_vtu_vid_write(chip, entry->valid, 0); if (err) return err; err = mv88e6xxx_g1_vtu_sid_write(chip, entry->sid); if (err) return err; if (entry->valid) { err = mv88e6390_g1_vtu_data_write(chip, entry->state); if (err) return err; } /* Load/Purge STU entry */ return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE); } /* VTU Violation Management */ static irqreturn_t mv88e6xxx_g1_vtu_prob_irq_thread_fn(int irq, void *dev_id) { struct mv88e6xxx_chip *chip = dev_id; u16 val, vid; int spid; int err; mv88e6xxx_reg_lock(chip); err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION); if (err) goto out; err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val); if (err) goto out; err = mv88e6xxx_g1_vtu_vid_read(chip, NULL, &vid); if (err) goto out; spid = val & MV88E6XXX_G1_VTU_OP_SPID_MASK; if (val & MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION) { trace_mv88e6xxx_vtu_member_violation(chip->dev, spid, vid); chip->ports[spid].vtu_member_violation++; } if (val & MV88E6XXX_G1_VTU_OP_MISS_VIOLATION) { trace_mv88e6xxx_vtu_miss_violation(chip->dev, spid, vid); chip->ports[spid].vtu_miss_violation++; } mv88e6xxx_reg_unlock(chip); return IRQ_HANDLED; out: mv88e6xxx_reg_unlock(chip); dev_err(chip->dev, "VTU problem: error %d while handling interrupt\n", err); return IRQ_HANDLED; } int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip) { int err; chip->vtu_prob_irq = irq_find_mapping(chip->g1_irq.domain, MV88E6XXX_G1_STS_IRQ_VTU_PROB); if (chip->vtu_prob_irq < 0) return chip->vtu_prob_irq; snprintf(chip->vtu_prob_irq_name, sizeof(chip->vtu_prob_irq_name), "mv88e6xxx-%s-g1-vtu-prob", dev_name(chip->dev)); err = request_threaded_irq(chip->vtu_prob_irq, NULL, mv88e6xxx_g1_vtu_prob_irq_thread_fn, IRQF_ONESHOT, chip->vtu_prob_irq_name, chip); if (err) irq_dispose_mapping(chip->vtu_prob_irq); return err; } void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip) { free_irq(chip->vtu_prob_irq, chip); irq_dispose_mapping(chip->vtu_prob_irq); } |