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All rights reserved. * Copyright (c) 2020, Linaro Ltd. */ #include <dt-bindings/clock/qcom,gcc-sdx55.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,sdx55.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { #address-cells = <1>; #size-cells = <1>; qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; interrupt-parent = <&intc>; memory { device_type = "memory"; reg = <0 0>; }; clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <38400000>; clock-output-names = "xo_board"; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; nand_clk_dummy: nand-clk-dummy { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX55_CX>; power-domain-names = "rpmhpd"; operating-points-v2 = <&cpu_opp_table>; }; }; firmware { scm { compatible = "qcom,scm-sdx55", "qcom,scm"; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp-345600000 { opp-hz = /bits/ 64 <345600000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-576000000 { opp-hz = /bits/ 64 <576000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; required-opps = <&rpmhpd_opp_nom>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; required-opps = <&rpmhpd_opp_turbo>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; hyp_mem: memory@8fc00000 { no-map; reg = <0x8fc00000 0x80000>; }; ac_db_mem: memory@8fc80000 { no-map; reg = <0x8fc80000 0x40000>; }; secdata_mem: memory@8fcfd000 { no-map; reg = <0x8fcfd000 0x1000>; }; sbl_mem: memory@8fd00000 { no-map; reg = <0x8fd00000 0x100000>; }; aop_image: memory@8fe00000 { no-map; reg = <0x8fe00000 0x20000>; }; aop_cmd_db: memory@8fe20000 { compatible = "qcom,cmd-db"; reg = <0x8fe20000 0x20000>; no-map; }; smem_mem: memory@8fe40000 { no-map; reg = <0x8fe40000 0xc0000>; }; tz_mem: memory@8ff00000 { no-map; reg = <0x8ff00000 0x100000>; }; tz_apps_mem: memory@90000000 { no-map; reg = <0x90000000 0x500000>; }; }; smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; ipa_smp2p_out: ipa-ap-to-modem { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; ipa_smp2p_in: ipa-modem-to-ap { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; soc: soc { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sdx55"; reg = <0x100000 0x1f0000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clock-names = "bi_tcxo", "sleep_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; }; blsp1_uart3: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x00831000 0x200>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc 30>, <&gcc 9>; clock-names = "core", "iface"; status = "disabled"; }; usb_hsphy: phy@ff4000 { compatible = "qcom,sdx55-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0x00ff4000 0x114>; status = "disabled"; #phy-cells = <0>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_BCR>; }; usb_qmpphy: phy@ff6000 { compatible = "qcom,sdx55-qmp-usb3-uni-phy"; reg = <0x00ff6000 0x1000>; clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, <&gcc GCC_USB3_PHY_PIPE_CLK>; clock-names = "aux", "ref", "cfg_ahb", "pipe"; clock-output-names = "usb3_uni_phy_pipe_clk_src"; #clock-cells = <0>; #phy-cells = <0>; resets = <&gcc GCC_USB3_PHY_BCR>, <&gcc GCC_USB3PHY_PHY_BCR>; reset-names = "phy", "phy_phy"; status = "disabled"; }; mc_virt: interconnect@1100000 { compatible = "qcom,sdx55-mc-virt"; reg = <0x01100000 0x400000>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; mem_noc: interconnect@9680000 { compatible = "qcom,sdx55-mem-noc"; reg = <0x09680000 0x40000>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@162c000 { compatible = "qcom,sdx55-system-noc"; reg = <0x0162c000 0x31200>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; qpic_bam: dma-controller@1b04000 { compatible = "qcom,bam-v1.7.0"; reg = <0x01b04000 0x1c000>; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rpmhcc RPMH_QPIC_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; status = "disabled"; }; qpic_nand: nand-controller@1b30000 { compatible = "qcom,sdx55-nand"; reg = <0x01b30000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&rpmhcc RPMH_QPIC_CLK>, <&nand_clk_dummy>; clock-names = "core", "aon"; dmas = <&qpic_bam 0>, <&qpic_bam 1>, <&qpic_bam 2>; dma-names = "tx", "rx", "cmd"; status = "disabled"; }; pcie_rc: pcie@1c00000 { compatible = "qcom,pcie-sdx55"; reg = <0x01c00000 0x3000>, <0x40000000 0xf1d>, <0x40000f20 0xc8>, <0x40001000 0x1000>, <0x40100000 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_PIPE_CLK>, <&gcc GCC_PCIE_AUX_CLK>, <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_MSTR_AXI_CLK>, <&gcc GCC_PCIE_SLV_AXI_CLK>, <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "sleep"; assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; assigned-clock-rates = <19200000>; iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x200 &apps_smmu 0x0202 0x1>, <0x300 &apps_smmu 0x0203 0x1>, <0x400 &apps_smmu 0x0204 0x1>; resets = <&gcc GCC_PCIE_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_GDSC>; phys = <&pcie_phy>; phy-names = "pciephy"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, <0x40000000 0xf1d>, <0x40000f20 0xc8>, <0x40001000 0x1000>, <0x40200000 0x100000>, <0x01c03000 0x3000>; reg-names = "parf", "dbi", "elbi", "atu", "addr_space", "mmio"; qcom,perst-regs = <&tcsr 0xb258 0xb270>; clocks = <&gcc GCC_PCIE_AUX_CLK>, <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_MSTR_AXI_CLK>, <&gcc GCC_PCIE_SLV_AXI_CLK>, <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "sleep", "ref"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "global", "doorbell"; interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; interconnect-names = "pcie-mem"; resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; phys = <&pcie_phy>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; status = "disabled"; }; pcie_phy: phy@1c06000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c06000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>, <&gcc GCC_PCIE_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; clock-output-names = "pcie_pipe_clk"; #clock-cells = <0>; #phy-cells = <0>; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; assigned-clock-rates = <100000000>; status = "disabled"; }; ipa: ipa@1e40000 { compatible = "qcom,sdx55-ipa"; iommus = <&apps_smmu 0x5e0 0x0>, <&apps_smmu 0x5e2 0x0>; reg = <0x1e40000 0x7000>, <0x1e50000 0x4b20>, <0x1e04000 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", "gsi", "ipa-clock-query", "ipa-setup-ready"; clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; interconnect-names = "memory", "imem", "config"; qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; status = "disabled"; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; #hwlock-cells = <1>; }; tcsr: syscon@1fc0000 { compatible = "qcom,sdx55-tcsr", "syscon"; reg = <0x01fc0000 0x1000>; }; sdhc_1: mmc@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>; clock-names = "iface", "core"; status = "disabled"; }; remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SDX55_CX>, <&rpmhpd SDX55_MSS>; power-domain-names = "cx", "mss"; qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; label = "mpss"; qcom,remote-pid = <1>; mboxes = <&apcs 15>; }; }; usb: usb@a6f8800 { compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; reg = <0x0a6f8800 0x400>; status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_USB30_MSTR_AXI_CLK>, <&gcc GCC_USB30_SLEEP_CLK>, <&gcc GCC_USB30_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 51 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_GDSC>; resets = <&gcc GCC_USB30_BCR>; usb_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; }; pdc: interrupt-controller@b210000 { compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>; qcom,pdc-ranges = <0 179 52>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; restart@c264000 { compatible = "qcom,pshold"; reg = <0x0c264000 0x1000>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0c440000 0x0000d00>, <0x0c600000 0x2000000>, <0x0e600000 0x0100000>, <0x0e700000 0x00a0000>, <0x0c40a000 0x0000700>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; tlmm: pinctrl@f100000 { compatible = "qcom,sdx55-pinctrl"; reg = <0xf100000 0x300000>; interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 108>; }; sram@1468f000 { compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; reg = <0x1468f000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1468f000 0x1000>; pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0x200>; }; }; apps_smmu: iommu@15000000 { compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x15000000 0x20000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; }; intc: interrupt-controller@17800000 { compatible = "qcom,msm-qgic2"; interrupt-controller; interrupt-parent = <&intc>; #interrupt-cells = <3>; reg = <0x17800000 0x1000>, <0x17802000 0x1000>; }; a7pll: clock@17808000 { compatible = "qcom,sdx55-a7pll"; reg = <0x17808000 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <0>; }; apcs: mailbox@17810000 { compatible = "qcom,sdx55-apcs-gcc", "syscon"; reg = <0x17810000 0x2000>; #mbox-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; clock-names = "ref", "pll", "aux"; #clock-cells = <0>; }; watchdog@17817000 { compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; reg = <0x17817000 0x1000>; clocks = <&sleep_clk>; }; timer@17820000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0x17820000 0x1000>; clock-frequency = <19200000>; frame@17821000 { frame-number = <0>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17821000 0x1000>, <0x17822000 0x1000>; }; frame@17823000 { frame-number = <1>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17823000 0x1000>; status = "disabled"; }; frame@17824000 { frame-number = <2>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17824000 0x1000>; status = "disabled"; }; frame@17825000 { frame-number = <3>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17825000 0x1000>; status = "disabled"; }; frame@17826000 { frame-number = <4>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17826000 0x1000>; status = "disabled"; }; frame@17827000 { frame-number = <5>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17827000 0x1000>; status = "disabled"; }; frame@17828000 { frame-number = <6>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17828000 0x1000>; status = "disabled"; }; frame@17829000 { frame-number = <7>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17829000 0x1000>; status = "disabled"; }; }; apps_rsc: rsc@17830000 { compatible = "qcom,rpmh-rsc"; reg = <0x17830000 0x10000>, <0x17840000 0x10000>; reg-names = "drv-0", "drv-1"; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; qcom,tcs-offset = <0xd00>; qcom,drv-id = <1>; qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>, <WAKE_TCS 2>, <CONTROL_TCS 1>; rpmhcc: clock-controller { compatible = "qcom,sdx55-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board>; }; rpmhpd: power-controller { compatible = "qcom,sdx55-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; }; rpmhpd_opp_min_svs: opp2 { opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; rpmhpd_opp_low_svs: opp3 { opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; rpmhpd_opp_svs: opp4 { opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; rpmhpd_opp_svs_l1: opp5 { opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; }; rpmhpd_opp_nom: opp6 { opp-level = <RPMH_REGULATOR_LEVEL_NOM>; }; rpmhpd_opp_nom_l1: opp7 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; }; rpmhpd_opp_nom_l2: opp8 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; }; rpmhpd_opp_turbo: opp9 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; }; rpmhpd_opp_turbo_l1: opp10 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; }; }; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; }; timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <19200000>; }; }; |