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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2022 Broadcom Ltd. */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "brcm,bcm4912", "brcm,bcmbca"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <2>; #size-cells = <0>; B53_0: cpu@0 { compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; }; B53_1: cpu@1 { compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x1>; next-level-cache = <&L2_0>; enable-method = "psci"; }; B53_2: cpu@2 { compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x2>; next-level-cache = <&L2_0>; enable-method = "psci"; }; B53_3: cpu@3 { compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x3>; next-level-cache = <&L2_0>; enable-method = "psci"; }; L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; pmu: pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&B53_0>, <&B53_1>, <&B53_2>, <&B53_3>; }; clocks: clocks { periph_clk: periph-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clocks = <&periph_clk>; clock-div = <4>; clock-mult = <1>; }; hsspi_pll: hsspi-pll { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; axi@81000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x81000000 0x8000>; gic: interrupt-controller@1000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; reg = <0x1000 0x1000>, <0x2000 0x2000>, <0x4000 0x2000>, <0x6000 0x2000>; }; }; bus@ff800000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1"; reg = <0x1000 0x600>, <0x2610 0x4>; reg-names = "hsspi", "spim-ctrl"; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&hsspi_pll &hsspi_pll>; clock-names = "hsspi", "pll"; num-cs = <8>; status = "disabled"; }; nand_controller: nand-controller@1800 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; reg = <0x1800 0x600>, <0x2000 0x10>; reg-names = "nand", "nand-int-base"; status = "disabled"; nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; }; }; uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart_clk>, <&uart_clk>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; }; }; |