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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> */ #include <dt-bindings/clock/bcm-nsp.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; }; chipcommon-a-bus@18000000 { compatible = "simple-bus"; ranges = <0x00000000 0x18000000 0x00001000>; #address-cells = <1>; #size-cells = <1>; uart0: serial@300 { compatible = "ns16550"; reg = <0x0300 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&iprocslow>; status = "disabled"; }; uart1: serial@400 { compatible = "ns16550"; reg = <0x0400 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&iprocslow>; pinctrl-names = "default"; pinctrl-0 = <&pinmux_uart1>; status = "disabled"; }; }; mpcore-bus@19000000 { compatible = "simple-bus"; ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; #size-cells = <1>; scu@20000 { compatible = "arm,cortex-a9-scu"; reg = <0x20000 0x100>; }; timer@20200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x20200 0x100>; interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; clocks = <&periph_clk>; }; timer@20600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x20600 0x20>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&periph_clk>; }; gic: interrupt-controller@21000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x21000 0x1000>, <0x20100 0x100>; }; L2: cache-controller@22000 { compatible = "arm,pl310-cache"; reg = <0x22000 0x1000>; cache-unified; arm,shared-override; prefetch-data = <1>; prefetch-instr = <1>; cache-level = <2>; }; }; axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; ranges = <0x00000000 0x18000000 0x00100000>; #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <1>; interrupt-map-mask = <0x000fffff 0xffff>; interrupt-map = /* ChipCommon */ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, /* Switch Register Access Block */ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, /* PCIe Controller 0 */ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, /* PCIe Controller 1 */ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, /* PCIe Controller 2 */ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* USB 2.0 Controller */ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* USB 3.0 Controller */ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 0 */ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 1 */ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 2 */ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 3 */ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* NAND Controller */ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; chipcommon: chipcommon@0 { reg = <0x00000000 0x1000>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; pcie0: pcie@12000 { reg = <0x00012000 0x1000>; #address-cells = <3>; #size-cells = <2>; }; pcie1: pcie@13000 { reg = <0x00013000 0x1000>; #address-cells = <3>; #size-cells = <2>; }; pcie2: pcie@14000 { reg = <0x00014000 0x1000>; #address-cells = <3>; #size-cells = <2>; }; usb2: usb2@21000 { reg = <0x00021000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; interrupt-parent = <&gic>; ehci: usb@21000 { compatible = "generic-ehci"; reg = <0x00021000 0x1000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb2_phy>; #address-cells = <1>; #size-cells = <0>; ehci_port1: port@1 { reg = <1>; #trigger-source-cells = <0>; }; ehci_port2: port@2 { reg = <2>; #trigger-source-cells = <0>; }; }; ohci: usb@22000 { compatible = "generic-ohci"; reg = <0x00022000 0x1000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ohci_port1: port@1 { reg = <1>; #trigger-source-cells = <0>; }; ohci_port2: port@2 { reg = <2>; #trigger-source-cells = <0>; }; }; }; usb3: usb3@23000 { reg = <0x00023000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; interrupt-parent = <&gic>; xhci: usb@23000 { compatible = "generic-xhci"; reg = <0x00023000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy>; phy-names = "usb"; #address-cells = <1>; #size-cells = <0>; xhci_port1: port@1 { reg = <1>; #trigger-source-cells = <0>; }; }; }; gmac0: ethernet@24000 { reg = <0x24000 0x800>; phy-mode = "internal"; fixed-link { speed = <1000>; full-duplex; }; }; gmac1: ethernet@25000 { reg = <0x25000 0x800>; phy-mode = "internal"; fixed-link { speed = <1000>; full-duplex; }; }; gmac2: ethernet@26000 { reg = <0x26000 0x800>; phy-mode = "internal"; fixed-link { speed = <1000>; full-duplex; }; }; gmac3: ethernet@27000 { reg = <0x27000 0x800>; }; }; pwm: pwm@18002000 { compatible = "brcm,iproc-pwm"; reg = <0x18002000 0x28>; clocks = <&osc>; #pwm-cells = <3>; status = "disabled"; }; mdio: mdio@18003000 { compatible = "brcm,iproc-mdio"; reg = <0x18003000 0x8>; #size-cells = <0>; #address-cells = <1>; }; mdio-mux@18003000 { compatible = "mdio-mux-mmioreg", "mdio-mux"; mdio-parent-bus = <&mdio>; #address-cells = <1>; #size-cells = <0>; reg = <0x18003000 0x4>; mux-mask = <0x200>; mdio@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; usb3_phy: usb3-phy@10 { compatible = "brcm,ns-ax-usb3-phy"; reg = <0x10>; usb3-dmp-syscon = <&usb3_dmp>; #phy-cells = <0>; status = "disabled"; }; }; }; rng: rng@18004000 { compatible = "brcm,bcm5301x-rng"; reg = <0x18004000 0x14>; }; srab: ethernet-switch@18007000 { compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { reg = <1>; }; port@2 { reg = <2>; }; port@3 { reg = <3>; }; port@4 { reg = <4>; }; port@5 { reg = <5>; ethernet = <&gmac0>; }; port@7 { reg = <7>; ethernet = <&gmac1>; }; port@8 { reg = <8>; ethernet = <&gmac2>; fixed-link { speed = <1000>; full-duplex; }; }; }; }; uart2: serial@18008000 { compatible = "ns16550a"; reg = <0x18008000 0x20>; clocks = <&iprocslow>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; status = "disabled"; }; dmu-bus@1800c000 { compatible = "simple-bus"; ranges = <0 0x1800c000 0x1000>; #address-cells = <1>; #size-cells = <1>; cru-bus@100 { compatible = "brcm,ns-cru", "simple-mfd"; reg = <0x100 0x1a4>; ranges; #address-cells = <1>; #size-cells = <1>; usb2_phy: phy@164 { compatible = "brcm,ns-usb2-phy"; reg = <0x164 0x4>; brcm,syscon-clkset = <&cru_clkset>; clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; clock-names = "phy-ref-clk"; #phy-cells = <0>; }; cru_clkset: syscon@180 { compatible = "brcm,cru-clkset", "syscon"; reg = <0x180 0x4>; }; pinctrl: pinctrl@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; reg-names = "cru_gpio_control"; spi-pins { groups = "spi_grp"; function = "spi"; }; pinmux_i2c: i2c-pins { groups = "i2c_grp"; function = "i2c"; }; pinmux_pwm: pwm-pins { groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; function = "pwm"; }; pinmux_uart1: uart1-pins { groups = "uart1_grp"; function = "uart1"; }; }; thermal: thermal@2c0 { compatible = "brcm,ns-thermal"; reg = <0x2c0 0x10>; #thermal-sensor-cells = <0>; }; }; }; nand_controller: nand-controller@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; reg-names = "nand", "iproc-idm", "iproc-ext"; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; brcm,nand-has-wp; }; usb3_dmp: syscon@18105000 { reg = <0x18105000 0x1000>; }; thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; polling-delay = <1000>; coefficients = <(-556) 418000>; thermal-sensors = <&thermal>; trips { cpu-crit { temperature = <125000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { }; }; }; }; |