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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 | /***********************license start*************** * Author: Cavium Networks * * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * * Copyright (c) 2003-2009 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as * published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful, but * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or * NONINFRINGEMENT. See the GNU General Public License for more * details. * * You should have received a copy of the GNU General Public License * along with this file; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * or visit http://www.gnu.org/licenses/. * * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information ***********************license end**************************************/ /** * Typedefs and defines for working with Octeon physical addresses. * */ #ifndef __CVMX_ADDRESS_H__ #define __CVMX_ADDRESS_H__ #if 0 typedef enum { CVMX_MIPS_SPACE_XKSEG = 3LL, CVMX_MIPS_SPACE_XKPHYS = 2LL, CVMX_MIPS_SPACE_XSSEG = 1LL, CVMX_MIPS_SPACE_XUSEG = 0LL } cvmx_mips_space_t; #endif typedef enum { CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL } cvmx_mips_xkseg_space_t; /* decodes <14:13> of a kseg3 window address */ typedef enum { CVMX_ADD_WIN_SCR = 0L, /* see cvmx_add_win_dma_dec_t for further decode */ CVMX_ADD_WIN_DMA = 1L, CVMX_ADD_WIN_UNUSED = 2L, CVMX_ADD_WIN_UNUSED2 = 3L } cvmx_add_win_dec_t; /* decode within DMA space */ typedef enum { /* * Add store data to the write buffer entry, allocating it if * necessary. */ CVMX_ADD_WIN_DMA_ADD = 0L, /* send out the write buffer entry to DRAM */ CVMX_ADD_WIN_DMA_SENDMEM = 1L, /* store data must be normal DRAM memory space address in this case */ /* send out the write buffer entry as an IOBDMA command */ CVMX_ADD_WIN_DMA_SENDDMA = 2L, /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ /* send out the write buffer entry as an IO write */ CVMX_ADD_WIN_DMA_SENDIO = 3L, /* store data must be normal IO space address in this case */ /* send out a single-tick command on the NCB bus */ CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, /* no write buffer data needed/used */ } cvmx_add_win_dma_dec_t; /* * Physical Address Decode * * Octeon-I HW never interprets this X (<39:36> reserved * for future expansion), software should set to 0. * * - 0x0 XXX0 0000 0000 to DRAM Cached * - 0x0 XXX0 0FFF FFFF * * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) * * - 0x0 XXX0 2000 0000 to DRAM Cached * - 0x0 XXXF FFFF FFFF * * - 0x1 00X0 0000 0000 to Boot Bus Uncached * - 0x1 00XF FFFF FFFF * * - 0x1 01X0 0000 0000 to Other NCB Uncached * - 0x1 FFXF FFFF FFFF devices * * Decode of all Octeon addresses */ typedef union { uint64_t u64; #ifdef __BIG_ENDIAN_BITFIELD /* mapped or unmapped virtual address */ struct { uint64_t R:2; uint64_t offset:62; } sva; /* mapped USEG virtual addresses (typically) */ struct { uint64_t zeroes:33; uint64_t offset:31; } suseg; /* mapped or unmapped virtual address */ struct { uint64_t ones:33; uint64_t sp:2; uint64_t offset:29; } sxkseg; /* * physical address accessed through xkphys unmapped virtual * address. */ struct { uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ uint64_t cca:3; /* ignored by octeon */ uint64_t mbz:10; uint64_t pa:49; /* physical address */ } sxkphys; /* physical address */ struct { uint64_t mbz:15; /* if set, the address is uncached and resides on MCB bus */ uint64_t is_io:1; /* * the hardware ignores this field when is_io==0, else * device ID. */ uint64_t did:8; /* the hardware ignores <39:36> in Octeon I */ uint64_t unaddr:4; uint64_t offset:36; } sphys; /* physical mem address */ struct { /* technically, <47:40> are dont-cares */ uint64_t zeroes:24; /* the hardware ignores <39:36> in Octeon I */ uint64_t unaddr:4; uint64_t offset:36; } smem; /* physical IO address */ struct { uint64_t mem_region:2; uint64_t mbz:13; /* 1 in this case */ uint64_t is_io:1; /* * The hardware ignores this field when is_io==0, else * device ID. */ uint64_t did:8; /* the hardware ignores <39:36> in Octeon I */ uint64_t unaddr:4; uint64_t offset:36; } sio; /* * Scratchpad virtual address - accessed through a window at * the end of kseg3 */ struct { uint64_t ones:49; /* CVMX_ADD_WIN_SCR (0) in this case */ cvmx_add_win_dec_t csrdec:2; uint64_t addr:13; } sscr; /* there should only be stores to IOBDMA space, no loads */ /* * IOBDMA virtual address - accessed through a window at the * end of kseg3 */ struct { uint64_t ones:49; uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ uint64_t unused2:3; uint64_t type:3; uint64_t addr:7; } sdma; struct { uint64_t didspace:24; uint64_t unused:40; } sfilldidspace; #else struct { uint64_t offset:62; uint64_t R:2; } sva; struct { uint64_t offset:31; uint64_t zeroes:33; } suseg; struct { uint64_t offset:29; uint64_t sp:2; uint64_t ones:33; } sxkseg; struct { uint64_t pa:49; uint64_t mbz:10; uint64_t cca:3; uint64_t R:2; } sxkphys; struct { uint64_t offset:36; uint64_t unaddr:4; uint64_t did:8; uint64_t is_io:1; uint64_t mbz:15; } sphys; struct { uint64_t offset:36; uint64_t unaddr:4; uint64_t zeroes:24; } smem; struct { uint64_t offset:36; uint64_t unaddr:4; uint64_t did:8; uint64_t is_io:1; uint64_t mbz:13; uint64_t mem_region:2; } sio; struct { uint64_t addr:13; cvmx_add_win_dec_t csrdec:2; uint64_t ones:49; } sscr; struct { uint64_t addr:7; uint64_t type:3; uint64_t unused2:3; uint64_t csrdec:2; uint64_t ones:49; } sdma; struct { uint64_t unused:40; uint64_t didspace:24; } sfilldidspace; #endif } cvmx_addr_t; /* These macros for used by 32 bit applications */ #define CVMX_MIPS32_SPACE_KSEG0 1l #define CVMX_ADD_SEG32(segment, add) \ (((int32_t)segment << 31) | (int32_t)(add)) /* * Currently all IOs are performed using XKPHYS addressing. Linux uses * the CvmMemCtl register to enable XKPHYS addressing to IO space from * user mode. Future OSes may need to change the upper bits of IO * addresses. The following define controls the upper two bits for all * IO addresses generated by the simple executive library. */ #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS /* These macros simplify the process of creating common IO addresses */ #define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) #ifndef CVMX_ADD_IO_SEG #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) #endif #define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) #define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) #define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) /* from include/ncb_rsl_id.v */ #define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ #define CVMX_OCT_DID_GMX0 1ULL #define CVMX_OCT_DID_GMX1 2ULL #define CVMX_OCT_DID_PCI 3ULL #define CVMX_OCT_DID_KEY 4ULL #define CVMX_OCT_DID_FPA 5ULL #define CVMX_OCT_DID_DFA 6ULL #define CVMX_OCT_DID_ZIP 7ULL #define CVMX_OCT_DID_RNG 8ULL #define CVMX_OCT_DID_IPD 9ULL #define CVMX_OCT_DID_PKT 10ULL #define CVMX_OCT_DID_TIM 11ULL #define CVMX_OCT_DID_TAG 12ULL /* the rest are not on the IO bus */ #define CVMX_OCT_DID_L2C 16ULL #define CVMX_OCT_DID_LMC 17ULL #define CVMX_OCT_DID_SPX0 18ULL #define CVMX_OCT_DID_SPX1 19ULL #define CVMX_OCT_DID_PIP 20ULL #define CVMX_OCT_DID_ASX0 22ULL #define CVMX_OCT_DID_ASX1 23ULL #define CVMX_OCT_DID_IOB 30ULL #define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) #define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) #define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) #define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) #define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) #define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) #define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) #define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) #define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) #define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) #define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) #define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) #define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) #define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) #define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) #define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) #define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) #endif /* __CVMX_ADDRESS_H__ */ |