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2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 | // SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family Main Domain peripherals * * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-ti.h> #include <dt-bindings/mux/mux.h> #include "k3-serdes.h" / { cmn_refclk: clock-cmnrefclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; cmn_refclk1: clock-cmnrefclk1 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; reg = <0x0 0x70000000 0x0 0x800000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x70000000 0x800000>; atf-sram@0 { reg = <0x0 0x20000>; }; }; scm_conf: scm-conf@100000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x50>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; }; cpsw0_phy_gmii_sel: phy@4044 { compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; ti,qsgmii-main-ports = <2>, <2>; reg = <0x4044 0x20>; #phy-cells = <1>; }; usb_serdes_mux: mux-controller@4000 { compatible = "reg-mux"; reg = <0x4000 0x20>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ }; ehrpwm_tbclk: clock-controller@4140 { compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; }; }; main_ehrpwm0: pwm@3000000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x00 0x3000000 0x00 0x100>; power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; clock-names = "tbclk", "fck"; status = "disabled"; }; main_ehrpwm1: pwm@3010000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x00 0x3010000 0x00 0x100>; power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; clock-names = "tbclk", "fck"; status = "disabled"; }; main_ehrpwm2: pwm@3020000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x00 0x3020000 0x00 0x100>; power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; clock-names = "tbclk", "fck"; status = "disabled"; }; main_ehrpwm3: pwm@3030000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x00 0x3030000 0x00 0x100>; power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; clock-names = "tbclk", "fck"; status = "disabled"; }; main_ehrpwm4: pwm@3040000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x00 0x3040000 0x00 0x100>; power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; clock-names = "tbclk", "fck"; status = "disabled"; }; main_ehrpwm5: pwm@3050000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x00 0x3050000 0x00 0x100>; power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; clock-names = "tbclk", "fck"; status = "disabled"; }; gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01900000 0x00 0x100000>, /* GICR */ <0x00 0x6f000000 0x00 0x2000>, /* GICC */ <0x00 0x6f010000 0x00 0x1000>, /* GICH */ <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; gic_its: msi-controller@1820000 { compatible = "arm,gic-v3-its"; reg = <0x00 0x01820000 0x00 0x10000>; socionext,synquacer-pre-its = <0x1000000 0x400000>; msi-controller; #msi-cells = <1>; }; }; main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <131>; ti,interrupt-ranges = <8 392 56>; }; main_navss: bus@30000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; dma-coherent; dma-ranges; ti,sci-dev-id = <199>; main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; reg = <0x0 0x310e0000 0x0 0x4000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <213>; ti,interrupt-ranges = <0 64 64>, <64 448 64>, <128 672 64>; }; main_udmass_inta: interrupt-controller@33d00000 { compatible = "ti,sci-inta"; reg = <0x0 0x33d00000 0x0 0x100000>; interrupt-controller; interrupt-parent = <&main_navss_intr>; msi-controller; #interrupt-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <209>; ti,interrupt-ranges = <0 0 256>; }; secure_proxy_main: mailbox@32c00000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; reg = <0x00 0x32c00000 0x00 0x100000>, <0x00 0x32400000 0x00 0x100000>, <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; }; smmu0: iommu@36600000 { compatible = "arm,smmu-v3"; reg = <0x0 0x36600000 0x0 0x100000>; interrupt-parent = <&gic500>; interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; interrupt-names = "eventq", "gerror"; #iommu-cells = <1>; }; hwspinlock: spinlock@30e00000 { compatible = "ti,am654-hwspinlock"; reg = <0x00 0x30e00000 0x00 0x1000>; #hwlock-cells = <1>; }; mailbox0_cluster0: mailbox@31f80000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f80000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f81000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f82000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f83000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f84000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f85000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f86000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f87000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f88000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f89000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f8a000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f8b000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, <0x0 0x33000000 0x0 0x40000>, <0x0 0x31080000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; ti,sci-dev-id = <211>; msi-parent = <&main_udmass_inta>; }; main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; reg = <0x0 0x31150000 0x0 0x100>, <0x0 0x34000000 0x0 0x100000>, <0x0 0x35000000 0x0 0x100000>, <0x0 0x30b00000 0x0 0x20000>, <0x0 0x30c00000 0x0 0x10000>, <0x0 0x30d00000 0x0 0x8000>; reg-names = "gcfg", "rchanrt", "tchanrt", "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <212>; ti,ringacc = <&main_ringacc>; ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ <0x0f>, /* TX_HCHAN */ <0x10>; /* TX_UHCHAN */ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ <0x0b>, /* RX_HCHAN */ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; cpts@310d0000 { compatible = "ti,j721e-cpts"; reg = <0x0 0x310d0000 0x0 0x400>; reg-names = "cpts"; clocks = <&k3_clks 201 1>; clock-names = "cpts"; interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; ti,cpts-ext-ts-inputs = <8>; }; }; cpsw0: ethernet@c000000 { compatible = "ti,j721e-cpswxg-nuss"; #address-cells = <2>; #size-cells = <2>; reg = <0x0 0xc000000 0x0 0x200000>; reg-names = "cpsw_nuss"; ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; clocks = <&k3_clks 19 89>; clock-names = "fck"; power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; dmas = <&main_udmap 0xca00>, <&main_udmap 0xca01>, <&main_udmap 0xca02>, <&main_udmap 0xca03>, <&main_udmap 0xca04>, <&main_udmap 0xca05>, <&main_udmap 0xca06>, <&main_udmap 0xca07>, <&main_udmap 0x4a00>; dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; status = "disabled"; ethernet-ports { #address-cells = <1>; #size-cells = <0>; cpsw0_port1: port@1 { reg = <1>; ti,mac-only; label = "port1"; status = "disabled"; }; cpsw0_port2: port@2 { reg = <2>; ti,mac-only; label = "port2"; status = "disabled"; }; cpsw0_port3: port@3 { reg = <3>; ti,mac-only; label = "port3"; status = "disabled"; }; cpsw0_port4: port@4 { reg = <4>; ti,mac-only; label = "port4"; status = "disabled"; }; cpsw0_port5: port@5 { reg = <5>; ti,mac-only; label = "port5"; status = "disabled"; }; cpsw0_port6: port@6 { reg = <6>; ti,mac-only; label = "port6"; status = "disabled"; }; cpsw0_port7: port@7 { reg = <7>; ti,mac-only; label = "port7"; status = "disabled"; }; cpsw0_port8: port@8 { reg = <8>; ti,mac-only; label = "port8"; status = "disabled"; }; }; cpsw9g_mdio: mdio@f00 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; reg = <0x0 0xf00 0x0 0x100>; #address-cells = <1>; #size-cells = <0>; clocks = <&k3_clks 19 89>; clock-names = "fck"; bus_freq = <1000000>; status = "disabled"; }; cpts@3d000 { compatible = "ti,j721e-cpts"; reg = <0x0 0x3d000 0x0 0x400>; clocks = <&k3_clks 19 16>; clock-names = "cpts"; interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; ti,cpts-periodic-outputs = <2>; }; }; main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x0 0x4e00000 0x0 0x1200>; power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; dma-names = "tx", "rx1", "rx2"; rng: rng@4e10000 { compatible = "inside-secure,safexcel-eip76"; reg = <0x0 0x4e10000 0x0 0x7d>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; }; }; main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x0 0x11c000 0x0 0x2b4>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { compatible = "pinctrl-single"; reg = <0x00 0x104200 0x00 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x00000007>; }; /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { compatible = "pinctrl-single"; reg = <0x00 0x104280 0x00 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000001f>; }; ti_csi2rx0: ticsi2rx@4500000 { compatible = "ti,j721e-csi2rx-shim"; reg = <0x0 0x4500000 0x0 0x1000>; ranges; #address-cells = <2>; #size-cells = <2>; dmas = <&main_udmap 0x4940>; dma-names = "rx0"; power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4504000 0x0 0x1000>; clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy0>; phy-names = "dphy"; ports { #address-cells = <1>; #size-cells = <0>; csi0_port0: port@0 { reg = <0>; status = "disabled"; }; csi0_port1: port@1 { reg = <1>; status = "disabled"; }; csi0_port2: port@2 { reg = <2>; status = "disabled"; }; csi0_port3: port@3 { reg = <3>; status = "disabled"; }; csi0_port4: port@4 { reg = <4>; status = "disabled"; }; }; }; }; ti_csi2rx1: ticsi2rx@4510000 { compatible = "ti,j721e-csi2rx-shim"; reg = <0x0 0x4510000 0x0 0x1000>; ranges; #address-cells = <2>; #size-cells = <2>; dmas = <&main_udmap 0x4960>; dma-names = "rx0"; power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4514000 0x0 0x1000>; clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy1>; phy-names = "dphy"; ports { #address-cells = <1>; #size-cells = <0>; csi1_port0: port@0 { reg = <0>; status = "disabled"; }; csi1_port1: port@1 { reg = <1>; status = "disabled"; }; csi1_port2: port@2 { reg = <2>; status = "disabled"; }; csi1_port3: port@3 { reg = <3>; status = "disabled"; }; csi1_port4: port@4 { reg = <4>; status = "disabled"; }; }; }; }; dphy0: phy@4580000 { compatible = "cdns,dphy-rx"; reg = <0x0 0x4580000 0x0 0x1100>; #phy-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; dphy1: phy@4590000 { compatible = "cdns,dphy-rx"; reg = <0x0 0x4590000 0x0 0x1100>; #phy-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; num-lanes = <2>; #reset-cells = <1>; ranges = <0x5000000 0x0 0x5000000 0x10000>; wiz0_pll0_refclk: pll0-refclk { clocks = <&k3_clks 292 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_pll1_refclk: pll1-refclk { clocks = <&k3_clks 292 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 0>; }; wiz0_refclk_dig: refclk-dig { clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { clocks = <&wiz0_refclk_dig>; #clock-cells = <0>; }; wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { clocks = <&wiz0_pll1_refclk>; #clock-cells = <0>; }; serdes0: serdes@5000000 { compatible = "ti,sierra-phy-t0"; reg-names = "serdes"; reg = <0x5000000 0x10000>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk"; }; }; serdes_wiz1: wiz@5010000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; num-lanes = <2>; #reset-cells = <1>; ranges = <0x5010000 0x0 0x5010000 0x10000>; wiz1_pll0_refclk: pll0-refclk { clocks = <&k3_clks 293 13>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll0_refclk>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_pll1_refclk: pll1-refclk { clocks = <&k3_clks 293 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&k3_clks 293 0>; }; wiz1_refclk_dig: refclk-dig { clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { clocks = <&wiz1_refclk_dig>; #clock-cells = <0>; }; wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { clocks = <&wiz1_pll1_refclk>; #clock-cells = <0>; }; serdes1: serdes@5010000 { compatible = "ti,sierra-phy-t0"; reg-names = "serdes"; reg = <0x5010000 0x10000>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk"; }; }; serdes_wiz2: wiz@5020000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; num-lanes = <2>; #reset-cells = <1>; ranges = <0x5020000 0x0 0x5020000 0x10000>; wiz2_pll0_refclk: pll0-refclk { clocks = <&k3_clks 294 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll0_refclk>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_pll1_refclk: pll1-refclk { clocks = <&k3_clks 294 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&k3_clks 294 0>; }; wiz2_refclk_dig: refclk-dig { clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { clocks = <&wiz2_refclk_dig>; #clock-cells = <0>; }; wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { clocks = <&wiz2_pll1_refclk>; #clock-cells = <0>; }; serdes2: serdes@5020000 { compatible = "ti,sierra-phy-t0"; reg-names = "serdes"; reg = <0x5020000 0x10000>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk"; }; }; serdes_wiz3: wiz@5030000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; num-lanes = <2>; #reset-cells = <1>; ranges = <0x5030000 0x0 0x5030000 0x10000>; wiz3_pll0_refclk: pll0-refclk { clocks = <&k3_clks 295 9>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll0_refclk>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_pll1_refclk: pll1-refclk { clocks = <&k3_clks 295 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll1_refclk>; assigned-clock-parents = <&k3_clks 295 0>; }; wiz3_refclk_dig: refclk-dig { clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_refclk_dig>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { clocks = <&wiz3_refclk_dig>; #clock-cells = <0>; }; wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { clocks = <&wiz3_pll1_refclk>; #clock-cells = <0>; }; serdes3: serdes@5030000 { compatible = "ti,sierra-phy-t0"; reg-names = "serdes"; reg = <0x5030000 0x10000>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk"; }; }; pcie0_rc: pcie@2900000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, <0x00 0x10000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 239 1>; clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; vendor-id = <0x104c>; device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; pcie1_rc: pcie@2910000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, <0x00 0x18000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 1>; clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; vendor-id = <0x104c>; device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x10000 0x10000>; dma-coherent; ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; pcie2_rc: pcie@2920000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02920000 0x00 0x1000>, <0x00 0x02927000 0x00 0x400>, <0x00 0x0e000000 0x00 0x00800000>, <0x44 0x00000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 241 1>; clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; vendor-id = <0x104c>; device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x20000 0x10000>; dma-coherent; ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; pcie3_rc: pcie@2930000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02930000 0x00 0x1000>, <0x00 0x02937000 0x00 0x400>, <0x00 0x0e800000 0x00 0x00800000>, <0x44 0x10000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 242 1>; clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; vendor-id = <0x104c>; device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x30000 0x10000>; dma-coherent; ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; serdes_wiz4: wiz@5050000 { compatible = "ti,am64-wiz-10g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 297 9>; assigned-clock-parents = <&k3_clks 297 10>; assigned-clock-rates = <19200000>; num-lanes = <4>; #reset-cells = <1>; #clock-cells = <1>; ranges = <0x05050000 0x00 0x05050000 0x010000>, <0x0a030a00 0x00 0x0a030a00 0x40>; serdes4: serdes@5050000 { /* * Note: we also map DPTX PHY registers as the Torrent * needs to manage those. */ compatible = "ti,j721e-serdes-10g"; reg = <0x05050000 0x010000>, <0x0a030a00 0x40>; /* DPTX PHY */ reg-names = "torrent_phy", "dptx_phy"; resets = <&serdes_wiz4 0>; reset-names = "torrent_reset"; clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; clock-names = "refclk"; assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; assigned-clock-parents = <&k3_clks 297 9>, <&k3_clks 297 9>, <&k3_clks 297 9>; #address-cells = <1>; #size-cells = <0>; }; }; main_timer0: timer@2400000 { compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 49 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 49 1>; assigned-clock-parents = <&k3_clks 49 2>; power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer1: timer@2410000 { compatible = "ti,am654-timer"; reg = <0x00 0x2410000 0x00 0x400>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 50 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer2: timer@2420000 { compatible = "ti,am654-timer"; reg = <0x00 0x2420000 0x00 0x400>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 51 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 51 1>; assigned-clock-parents = <&k3_clks 51 2>; power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer3: timer@2430000 { compatible = "ti,am654-timer"; reg = <0x00 0x2430000 0x00 0x400>; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 52 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer4: timer@2440000 { compatible = "ti,am654-timer"; reg = <0x00 0x2440000 0x00 0x400>; interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 53 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 53 1>; assigned-clock-parents = <&k3_clks 53 2>; power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer5: timer@2450000 { compatible = "ti,am654-timer"; reg = <0x00 0x2450000 0x00 0x400>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 54 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer6: timer@2460000 { compatible = "ti,am654-timer"; reg = <0x00 0x2460000 0x00 0x400>; interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 55 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 55 1>; assigned-clock-parents = <&k3_clks 55 2>; power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer7: timer@2470000 { compatible = "ti,am654-timer"; reg = <0x00 0x2470000 0x00 0x400>; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 57 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer8: timer@2480000 { compatible = "ti,am654-timer"; reg = <0x00 0x2480000 0x00 0x400>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 58 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 58 1>; assigned-clock-parents = <&k3_clks 58 2>; power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer9: timer@2490000 { compatible = "ti,am654-timer"; reg = <0x00 0x2490000 0x00 0x400>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 59 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer10: timer@24a0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24a0000 0x00 0x400>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 60 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 60 1>; assigned-clock-parents = <&k3_clks 60 2>; power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer11: timer@24b0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24b0000 0x00 0x400>; interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 62 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer12: timer@24c0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24c0000 0x00 0x400>; interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 63 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 63 1>; assigned-clock-parents = <&k3_clks 63 2>; power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer13: timer@24d0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24d0000 0x00 0x400>; interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 64 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer14: timer@24e0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24e0000 0x00 0x400>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 65 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 65 1>; assigned-clock-parents = <&k3_clks 65 2>; power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer15: timer@24f0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24f0000 0x00 0x400>; interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 66 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer16: timer@2500000 { compatible = "ti,am654-timer"; reg = <0x00 0x2500000 0x00 0x400>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 67 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 67 1>; assigned-clock-parents = <&k3_clks 67 2>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer17: timer@2510000 { compatible = "ti,am654-timer"; reg = <0x00 0x2510000 0x00 0x400>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 68 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer18: timer@2520000 { compatible = "ti,am654-timer"; reg = <0x00 0x2520000 0x00 0x400>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 69 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 69 1>; assigned-clock-parents = <&k3_clks 69 2>; power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer19: timer@2530000 { compatible = "ti,am654-timer"; reg = <0x00 0x2530000 0x00 0x400>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 70 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; status = "disabled"; }; main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 0>; clock-names = "fclk"; status = "disabled"; }; main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 0>; clock-names = "fclk"; status = "disabled"; }; main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 0>; clock-names = "fclk"; status = "disabled"; }; main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 0>; clock-names = "fclk"; status = "disabled"; }; main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 0>; clock-names = "fclk"; status = "disabled"; }; main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 0>; clock-names = "fclk"; status = "disabled"; }; main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 0>; clock-names = "fclk"; status = "disabled"; }; main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 0>; clock-names = "fclk"; status = "disabled"; }; main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 0>; clock-names = "fclk"; status = "disabled"; }; main_gpio0: gpio@600000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00600000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <256>, <257>, <258>, <259>, <260>, <261>, <262>, <263>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio1: gpio@601000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00601000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <288>, <289>, <290>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio2: gpio@610000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00610000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <264>, <265>, <266>, <267>, <268>, <269>, <270>, <271>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio3: gpio@611000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00611000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <292>, <293>, <294>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 108 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio4: gpio@620000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00620000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <272>, <273>, <274>, <275>, <276>, <277>, <278>, <279>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio5: gpio@621000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00621000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <296>, <297>, <298>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 110 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio6: gpio@630000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00630000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <280>, <281>, <282>, <283>, <284>, <285>, <286>, <287>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio7: gpio@631000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x00631000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <300>, <301>, <302>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 112 0>; clock-names = "gpio"; status = "disabled"; }; main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_ahb", "clk_xin"; clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; assigned-clocks = <&k3_clks 91 1>; assigned-clock-parents = <&k3_clks 91 2>; bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; ti,itap-del-sel-ddr52 = <0x3>; ti,trm-icp = <0x8>; dma-coherent; status = "disabled"; }; main_sdhci1: mmc@4fb0000 { compatible = "ti,j721e-sdhci-4bit"; reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_ahb", "clk_xin"; clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; ti,itap-del-sel-ddr50 = <0x2>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; sdhci-caps-mask = <0x2 0x0>; status = "disabled"; }; main_sdhci2: mmc@4f98000 { compatible = "ti,j721e-sdhci-4bit"; reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_ahb", "clk_xin"; clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; ti,itap-del-sel-ddr50 = <0x2>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; sdhci-caps-mask = <0x2 0x0>; status = "disabled"; }; usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; dma-coherent; power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; clock-names = "ref", "lpm"; assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ #address-cells = <2>; #size-cells = <2>; ranges; usb0: usb@6000000 { compatible = "cdns,usb3"; reg = <0x00 0x6000000 0x00 0x10000>, <0x00 0x6010000 0x00 0x10000>, <0x00 0x6020000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; }; }; usbss1: cdns-usb@4114000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4114000 0x00 0x100>; dma-coherent; power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; clock-names = "ref", "lpm"; assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ #address-cells = <2>; #size-cells = <2>; ranges; usb1: usb@6400000 { compatible = "cdns,usb3"; reg = <0x00 0x6400000 0x00 0x10000>, <0x00 0x6410000 0x00 0x10000>, <0x00 0x6420000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; }; }; main_i2c0: i2c@2000000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2000000 0x0 0x100>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 187 0>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; status = "disabled"; }; main_i2c1: i2c@2010000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2010000 0x0 0x100>; interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 188 0>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c2: i2c@2020000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2020000 0x0 0x100>; interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 189 0>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c3: i2c@2030000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2030000 0x0 0x100>; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 190 0>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c4: i2c@2040000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2040000 0x0 0x100>; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 191 0>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c5: i2c@2050000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2050000 0x0 0x100>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 192 0>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c6: i2c@2060000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2060000 0x0 0x100>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 193 0>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; ufs_wrapper: ufs-wrapper@4e80000 { compatible = "ti,j721e-ufs"; reg = <0x0 0x4e80000 0x0 0x100>; power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 277 1>; assigned-clocks = <&k3_clks 277 1>; assigned-clock-parents = <&k3_clks 277 4>; ranges; #address-cells = <2>; #size-cells = <2>; ufs@4e84000 { compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; reg = <0x0 0x4e84000 0x0 0x10000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; clock-names = "core_clk", "phy_clk", "ref_clk"; dma-coherent; }; }; mhdp: dp-bridge@a000000 { compatible = "ti,j721e-mhdp8546"; /* * Note: we do not map DPTX PHY area, as that is handled by * the PHY driver. */ reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ reg-names = "mhdptx", "j721e-intg"; clocks = <&k3_clks 151 36>; interrupt-parent = <&gic500>; interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; dp0_ports: ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@4 { reg = <4>; }; }; }; dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ <0x00 0x04af0000 0x00 0x10000>; /* wb */ reg-names = "common_m", "common_s0", "common_s1", "common_s2", "vidl1", "vidl2","vid1","vid2", "ovr1", "ovr2", "ovr3", "ovr4", "vp1", "vp2", "vp3", "vp4", "wb"; clocks = <&k3_clks 152 0>, <&k3_clks 152 1>, <&k3_clks 152 4>, <&k3_clks 152 9>, <&k3_clks 152 13>; clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common_m", "common_s0", "common_s1", "common_s2"; dss_ports: ports { }; }; mcasp0: mcasp@2b00000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b00000 0x0 0x2000>, <0x0 0x02b08000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; dma-names = "tx", "rx"; clocks = <&k3_clks 174 1>; clock-names = "fck"; power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp1: mcasp@2b10000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b10000 0x0 0x2000>, <0x0 0x02b18000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; dma-names = "tx", "rx"; clocks = <&k3_clks 175 1>; clock-names = "fck"; power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp2: mcasp@2b20000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b20000 0x0 0x2000>, <0x0 0x02b28000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; dma-names = "tx", "rx"; clocks = <&k3_clks 176 1>; clock-names = "fck"; power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp3: mcasp@2b30000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b30000 0x0 0x2000>, <0x0 0x02b38000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; dma-names = "tx", "rx"; clocks = <&k3_clks 177 1>; clock-names = "fck"; power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp4: mcasp@2b40000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b40000 0x0 0x2000>, <0x0 0x02b48000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; dma-names = "tx", "rx"; clocks = <&k3_clks 178 1>; clock-names = "fck"; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp5: mcasp@2b50000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b50000 0x0 0x2000>, <0x0 0x02b58000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; dma-names = "tx", "rx"; clocks = <&k3_clks 179 1>; clock-names = "fck"; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp6: mcasp@2b60000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b60000 0x0 0x2000>, <0x0 0x02b68000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; dma-names = "tx", "rx"; clocks = <&k3_clks 180 1>; clock-names = "fck"; power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp7: mcasp@2b70000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b70000 0x0 0x2000>, <0x0 0x02b78000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; dma-names = "tx", "rx"; clocks = <&k3_clks 181 1>; clock-names = "fck"; power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp8: mcasp@2b80000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b80000 0x0 0x2000>, <0x0 0x02b88000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; dma-names = "tx", "rx"; clocks = <&k3_clks 182 1>; clock-names = "fck"; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp9: mcasp@2b90000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b90000 0x0 0x2000>, <0x0 0x02b98000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; dma-names = "tx", "rx"; clocks = <&k3_clks 183 1>; clock-names = "fck"; power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp10: mcasp@2ba0000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02ba0000 0x0 0x2000>, <0x0 0x02ba8000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; dma-names = "tx", "rx"; clocks = <&k3_clks 184 1>; clock-names = "fck"; power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcasp11: mcasp@2bb0000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02bb0000 0x0 0x2000>, <0x0 0x02bb8000 0x0 0x1000>; reg-names = "mpu","dat"; interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; dma-names = "tx", "rx"; clocks = <&k3_clks 185 1>; clock-names = "fck"; power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; watchdog0: watchdog@2200000 { compatible = "ti,j7-rti-wdt"; reg = <0x0 0x2200000 0x0 0x100>; clocks = <&k3_clks 252 1>; power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 252 1>; assigned-clock-parents = <&k3_clks 252 5>; }; watchdog1: watchdog@2210000 { compatible = "ti,j7-rti-wdt"; reg = <0x0 0x2210000 0x0 0x100>; clocks = <&k3_clks 253 1>; power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 253 1>; assigned-clock-parents = <&k3_clks 253 5>; }; main_r5fss0: r5fss@5c00000 { compatible = "ti,j721e-r5fss"; ti,cluster-mode = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j721e-r5f"; reg = <0x5c00000 0x00008000>, <0x5c10000 0x00008000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <245>; ti,sci-proc-ids = <0x06 0xff>; resets = <&k3_reset 245 1>; firmware-name = "j7-main-r5f0_0-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; main_r5fss0_core1: r5f@5d00000 { compatible = "ti,j721e-r5f"; reg = <0x5d00000 0x00008000>, <0x5d10000 0x00008000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <246>; ti,sci-proc-ids = <0x07 0xff>; resets = <&k3_reset 246 1>; firmware-name = "j7-main-r5f0_1-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; }; main_r5fss1: r5fss@5e00000 { compatible = "ti,j721e-r5fss"; ti,cluster-mode = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; main_r5fss1_core0: r5f@5e00000 { compatible = "ti,j721e-r5f"; reg = <0x5e00000 0x00008000>, <0x5e10000 0x00008000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <247>; ti,sci-proc-ids = <0x08 0xff>; resets = <&k3_reset 247 1>; firmware-name = "j7-main-r5f1_0-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; main_r5fss1_core1: r5f@5f00000 { compatible = "ti,j721e-r5f"; reg = <0x5f00000 0x00008000>, <0x5f10000 0x00008000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <248>; ti,sci-proc-ids = <0x09 0xff>; resets = <&k3_reset 248 1>; firmware-name = "j7-main-r5f1_1-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; }; c66_0: dsp@4d80800000 { compatible = "ti,j721e-c66-dsp"; reg = <0x4d 0x80800000 0x00 0x00048000>, <0x4d 0x80e00000 0x00 0x00008000>, <0x4d 0x80f00000 0x00 0x00008000>; reg-names = "l2sram", "l1pram", "l1dram"; ti,sci = <&dmsc>; ti,sci-dev-id = <142>; ti,sci-proc-ids = <0x03 0xff>; resets = <&k3_reset 142 1>; firmware-name = "j7-c66_0-fw"; status = "disabled"; }; c66_1: dsp@4d81800000 { compatible = "ti,j721e-c66-dsp"; reg = <0x4d 0x81800000 0x00 0x00048000>, <0x4d 0x81e00000 0x00 0x00008000>, <0x4d 0x81f00000 0x00 0x00008000>; reg-names = "l2sram", "l1pram", "l1dram"; ti,sci = <&dmsc>; ti,sci-dev-id = <143>; ti,sci-proc-ids = <0x04 0xff>; resets = <&k3_reset 143 1>; firmware-name = "j7-c66_1-fw"; status = "disabled"; }; c71_0: dsp@64800000 { compatible = "ti,j721e-c71-dsp"; reg = <0x00 0x64800000 0x00 0x00080000>, <0x00 0x64e00000 0x00 0x0000c000>; reg-names = "l2sram", "l1dram"; ti,sci = <&dmsc>; ti,sci-dev-id = <15>; ti,sci-proc-ids = <0x30 0xff>; resets = <&k3_reset 15 1>; firmware-name = "j7-c71_0-fw"; status = "disabled"; }; icssg0: icssg@b000000 { compatible = "ti,j721e-icssg"; reg = <0x00 0xb000000 0x00 0x80000>; power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x0b000000 0x100000>; icssg0_mem: memories@0 { reg = <0x0 0x2000>, <0x2000 0x2000>, <0x10000 0x10000>; reg-names = "dram0", "dram1", "shrdram2"; }; icssg0_cfg: cfg@26000 { compatible = "ti,pruss-cfg", "syscon"; reg = <0x26000 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x2000>; clocks { #address-cells = <1>; #size-cells = <0>; icssg0_coreclk_mux: coreclk-mux@3c { reg = <0x3c>; #clock-cells = <0>; clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ <&k3_clks 119 1>; /* icssg0_iclk */ assigned-clocks = <&icssg0_coreclk_mux>; assigned-clock-parents = <&k3_clks 119 1>; }; icssg0_iepclk_mux: iepclk-mux@30 { reg = <0x30>; #clock-cells = <0>; clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ <&icssg0_coreclk_mux>; /* core_clk */ assigned-clocks = <&icssg0_iepclk_mux>; assigned-clock-parents = <&icssg0_coreclk_mux>; }; }; }; icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; }; icssg0_mii_g_rt: mii-g-rt@33000 { compatible = "ti,pruss-mii-g", "syscon"; reg = <0x33000 0x1000>; }; icssg0_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; interrupt-controller; #interrupt-cells = <3>; interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host_intr0", "host_intr1", "host_intr2", "host_intr3", "host_intr4", "host_intr5", "host_intr6", "host_intr7"; }; pru0_0: pru@34000 { compatible = "ti,j721e-pru"; reg = <0x34000 0x3000>, <0x22000 0x100>, <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-pru0_0-fw"; }; rtu0_0: rtu@4000 { compatible = "ti,j721e-rtu"; reg = <0x4000 0x2000>, <0x23000 0x100>, <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-rtu0_0-fw"; }; tx_pru0_0: txpru@a000 { compatible = "ti,j721e-tx-pru"; reg = <0xa000 0x1800>, <0x25000 0x100>, <0x25400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru0_0-fw"; }; pru0_1: pru@38000 { compatible = "ti,j721e-pru"; reg = <0x38000 0x3000>, <0x24000 0x100>, <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-pru0_1-fw"; }; rtu0_1: rtu@6000 { compatible = "ti,j721e-rtu"; reg = <0x6000 0x2000>, <0x23800 0x100>, <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-rtu0_1-fw"; }; tx_pru0_1: txpru@c000 { compatible = "ti,j721e-tx-pru"; reg = <0xc000 0x1800>, <0x25800 0x100>, <0x25c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru0_1-fw"; }; icssg0_mdio: mdio@32400 { compatible = "ti,davinci_mdio"; reg = <0x32400 0x100>; clocks = <&k3_clks 119 1>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; status = "disabled"; }; }; icssg1: icssg@b100000 { compatible = "ti,j721e-icssg"; reg = <0x00 0xb100000 0x00 0x80000>; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x0b100000 0x100000>; icssg1_mem: memories@b100000 { reg = <0x0 0x2000>, <0x2000 0x2000>, <0x10000 0x10000>; reg-names = "dram0", "dram1", "shrdram2"; }; icssg1_cfg: cfg@26000 { compatible = "ti,pruss-cfg", "syscon"; reg = <0x26000 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x2000>; clocks { #address-cells = <1>; #size-cells = <0>; icssg1_coreclk_mux: coreclk-mux@3c { reg = <0x3c>; #clock-cells = <0>; clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ <&k3_clks 120 4>; /* icssg1_iclk */ assigned-clocks = <&icssg1_coreclk_mux>; assigned-clock-parents = <&k3_clks 120 4>; }; icssg1_iepclk_mux: iepclk-mux@30 { reg = <0x30>; #clock-cells = <0>; clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ <&icssg1_coreclk_mux>; /* core_clk */ assigned-clocks = <&icssg1_iepclk_mux>; assigned-clock-parents = <&icssg1_coreclk_mux>; }; }; }; icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; }; icssg1_mii_g_rt: mii-g-rt@33000 { compatible = "ti,pruss-mii-g", "syscon"; reg = <0x33000 0x1000>; }; icssg1_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; interrupt-controller; #interrupt-cells = <3>; interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host_intr0", "host_intr1", "host_intr2", "host_intr3", "host_intr4", "host_intr5", "host_intr6", "host_intr7"; }; pru1_0: pru@34000 { compatible = "ti,j721e-pru"; reg = <0x34000 0x4000>, <0x22000 0x100>, <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-pru1_0-fw"; }; rtu1_0: rtu@4000 { compatible = "ti,j721e-rtu"; reg = <0x4000 0x2000>, <0x23000 0x100>, <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-rtu1_0-fw"; }; tx_pru1_0: txpru@a000 { compatible = "ti,j721e-tx-pru"; reg = <0xa000 0x1800>, <0x25000 0x100>, <0x25400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru1_0-fw"; }; pru1_1: pru@38000 { compatible = "ti,j721e-pru"; reg = <0x38000 0x4000>, <0x24000 0x100>, <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-pru1_1-fw"; }; rtu1_1: rtu@6000 { compatible = "ti,j721e-rtu"; reg = <0x6000 0x2000>, <0x23800 0x100>, <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-rtu1_1-fw"; }; tx_pru1_1: txpru@c000 { compatible = "ti,j721e-tx-pru"; reg = <0xc000 0x1800>, <0x25800 0x100>, <0x25c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru1_1-fw"; }; icssg1_mdio: mdio@32400 { compatible = "ti,davinci_mdio"; reg = <0x32400 0x100>; clocks = <&k3_clks 120 4>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; status = "disabled"; }; }; main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, <0x00 0x02708000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan1: can@2711000 { compatible = "bosch,m_can"; reg = <0x00 0x02711000 0x00 0x200>, <0x00 0x02718000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan2: can@2721000 { compatible = "bosch,m_can"; reg = <0x00 0x02721000 0x00 0x200>, <0x00 0x02728000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan3: can@2731000 { compatible = "bosch,m_can"; reg = <0x00 0x02731000 0x00 0x200>, <0x00 0x02738000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan4: can@2741000 { compatible = "bosch,m_can"; reg = <0x00 0x02741000 0x00 0x200>, <0x00 0x02748000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan5: can@2751000 { compatible = "bosch,m_can"; reg = <0x00 0x02751000 0x00 0x200>, <0x00 0x02758000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan6: can@2761000 { compatible = "bosch,m_can"; reg = <0x00 0x02761000 0x00 0x200>, <0x00 0x02768000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan7: can@2771000 { compatible = "bosch,m_can"; reg = <0x00 0x02771000 0x00 0x200>, <0x00 0x02778000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan8: can@2781000 { compatible = "bosch,m_can"; reg = <0x00 0x02781000 0x00 0x200>, <0x00 0x02788000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan9: can@2791000 { compatible = "bosch,m_can"; reg = <0x00 0x02791000 0x00 0x200>, <0x00 0x02798000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan10: can@27a1000 { compatible = "bosch,m_can"; reg = <0x00 0x027a1000 0x00 0x200>, <0x00 0x027a8000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan11: can@27b1000 { compatible = "bosch,m_can"; reg = <0x00 0x027b1000 0x00 0x200>, <0x00 0x027b8000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan12: can@27c1000 { compatible = "bosch,m_can"; reg = <0x00 0x027c1000 0x00 0x200>, <0x00 0x027c8000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_mcan13: can@27d1000 { compatible = "bosch,m_can"; reg = <0x00 0x027d1000 0x00 0x200>, <0x00 0x027d8000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; main_spi0: spi@2100000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02100000 0x00 0x400>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 266 1>; status = "disabled"; }; main_spi1: spi@2110000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02110000 0x00 0x400>; interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 267 1>; status = "disabled"; }; main_spi2: spi@2120000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02120000 0x00 0x400>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 268 1>; status = "disabled"; }; main_spi3: spi@2130000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02130000 0x00 0x400>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 269 1>; status = "disabled"; }; main_spi4: spi@2140000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02140000 0x00 0x400>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 270 1>; status = "disabled"; }; main_spi5: spi@2150000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02150000 0x00 0x400>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 271 1>; status = "disabled"; }; main_spi6: spi@2160000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02160000 0x00 0x400>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 272 1>; status = "disabled"; }; main_spi7: spi@2170000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02170000 0x00 0x400>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 273 1>; status = "disabled"; }; main_esm: esm@700000 { compatible = "ti,j721e-esm"; reg = <0x0 0x700000 0x0 0x1000>; ti,esm-pins = <344>, <345>; }; }; |