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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2019 MediaTek Inc. * Author: Mars.C <mars.cheng@mediatek.com> * */ #include <dt-bindings/clock/mt6779-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/mt6779-pinfunc.h> / { compatible = "mediatek,mt6779"; interrupt-parent = <&sysirq>; #address-cells = <2>; #size-cells = <2>; psci { compatible = "arm,psci-0.2"; method = "smc"; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x000>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x100>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x200>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x300>; }; cpu4: cpu@4 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x400>; }; cpu5: cpu@5 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x500>; }; cpu6: cpu@6 { device_type = "cpu"; compatible = "arm,cortex-a75"; enable-method = "psci"; reg = <0x600>; }; cpu7: cpu@7 { device_type = "cpu"; compatible = "arm,cortex-a75"; enable-method = "psci"; reg = <0x700>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; }; clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; clk32k: oscillator-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "clk32k"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges; gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x0c000000 0 0x40000>, /* GICD */ <0 0x0c040000 0 0x200000>; /* GICR */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; ppi-partitions { ppi_cluster0: interrupt-partition-0 { affinity = <&cpu0 &cpu1 \ &cpu2 &cpu3 &cpu4 &cpu5>; }; ppi_cluster1: interrupt-partition-1 { affinity = <&cpu6 &cpu7>; }; }; }; sysirq: intpol-controller@c53a650 { compatible = "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x0c53a650 0 0x50>; }; topckgen: clock-controller@10000000 { compatible = "mediatek,mt6779-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; }; infracfg_ao: clock-controller@10001000 { compatible = "mediatek,mt6779-infracfg_ao", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; }; pio: pinctrl@10005000 { compatible = "mediatek,mt6779-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x11c20000 0 0x1000>, <0 0x11d10000 0 0x1000>, <0 0x11e20000 0 0x1000>, <0 0x11e70000 0 0x1000>, <0 0x11ea0000 0 0x1000>, <0 0x11f20000 0 0x1000>, <0 0x11f30000 0 0x1000>, <0 0x1000b000 0 0x1000>; reg-names = "gpio", "iocfg_rm", "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", "iocfg_tl", "eint"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 210>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; }; apmixed: clock-controller@1000c000 { compatible = "mediatek,mt6779-apmixed", "syscon"; reg = <0 0x1000c000 0 0xe00>; #clock-cells = <1>; }; pwrap: pwrap@1000d000 { compatible = "mediatek,mt6779-pwrap"; reg = <0 0x1000d000 0 0x1000>; reg-names = "pwrap"; interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>; clock-names = "spi", "wrap"; }; devapc: devapc@10207000 { compatible = "mediatek,mt6779-devapc"; reg = <0 0x10207000 0 0x1000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>; clock-names = "devapc-infra-clock"; }; uart0: serial@11002000 { compatible = "mediatek,mt6779-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; clock-names = "baud", "bus"; status = "disabled"; }; uart1: serial@11003000 { compatible = "mediatek,mt6779-uart", "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; clock-names = "baud", "bus"; status = "disabled"; }; uart2: serial@11004000 { compatible = "mediatek,mt6779-uart", "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; clock-names = "baud", "bus"; status = "disabled"; }; audio: clock-controller@11210000 { compatible = "mediatek,mt6779-audio", "syscon"; reg = <0 0x11210000 0 0x1000>; #clock-cells = <1>; }; mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt6779-mfgcfg", "syscon"; reg = <0 0x13fbf000 0 0x1000>; #clock-cells = <1>; }; mmsys: syscon@14000000 { compatible = "mediatek,mt6779-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; imgsys: clock-controller@15020000 { compatible = "mediatek,mt6779-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; vdecsys: clock-controller@16000000 { compatible = "mediatek,mt6779-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; vencsys: clock-controller@17000000 { compatible = "mediatek,mt6779-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; }; camsys: clock-controller@1a000000 { compatible = "mediatek,mt6779-camsys", "syscon"; reg = <0 0x1a000000 0 0x10000>; #clock-cells = <1>; }; ipesys: clock-controller@1b000000 { compatible = "mediatek,mt6779-ipesys", "syscon"; reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; }; }; |