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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 | // SPDX-License-Identifier: GPL-2.0-only /* * Low-level device IO routines for ST-Ericsson CW1200 drivers * * Copyright (c) 2010, ST-Ericsson * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> * * Based on: * ST-Ericsson UMAC CW1200 driver, which is * Copyright (c) 2010, ST-Ericsson * Author: Ajitpal Singh <ajitpal.singh@lockless.no> */ #include <linux/types.h> #include "cw1200.h" #include "hwio.h" #include "hwbus.h" /* Sdio addr is 4*spi_addr */ #define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2) #define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \ ((((buf_id) & 0x1F) << 7) \ | (((mpf) & 1) << 6) \ | (((rfu) & 1) << 5) \ | (((reg_id_ofs) & 0x1F) << 0)) #define MAX_RETRY 3 static int __cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf, size_t buf_len, int buf_id) { u16 addr_sdio; u32 sdio_reg_addr_17bit; /* Check if buffer is aligned to 4 byte boundary */ if (WARN_ON(((unsigned long)buf & 3) && (buf_len > 4))) { pr_err("buffer is not aligned.\n"); return -EINVAL; } /* Convert to SDIO Register Address */ addr_sdio = SPI_REG_ADDR_TO_SDIO(addr); sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio); return priv->hwbus_ops->hwbus_memcpy_fromio(priv->hwbus_priv, sdio_reg_addr_17bit, buf, buf_len); } static int __cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf, size_t buf_len, int buf_id) { u16 addr_sdio; u32 sdio_reg_addr_17bit; /* Convert to SDIO Register Address */ addr_sdio = SPI_REG_ADDR_TO_SDIO(addr); sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio); return priv->hwbus_ops->hwbus_memcpy_toio(priv->hwbus_priv, sdio_reg_addr_17bit, buf, buf_len); } static inline int __cw1200_reg_read_32(struct cw1200_common *priv, u16 addr, u32 *val) { __le32 tmp; int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0); *val = le32_to_cpu(tmp); return i; } static inline int __cw1200_reg_write_32(struct cw1200_common *priv, u16 addr, u32 val) { __le32 tmp = cpu_to_le32(val); return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0); } static inline int __cw1200_reg_read_16(struct cw1200_common *priv, u16 addr, u16 *val) { __le16 tmp; int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0); *val = le16_to_cpu(tmp); return i; } static inline int __cw1200_reg_write_16(struct cw1200_common *priv, u16 addr, u16 val) { __le16 tmp = cpu_to_le16(val); return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0); } int cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf, size_t buf_len) { int ret; priv->hwbus_ops->lock(priv->hwbus_priv); ret = __cw1200_reg_read(priv, addr, buf, buf_len, 0); priv->hwbus_ops->unlock(priv->hwbus_priv); return ret; } int cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf, size_t buf_len) { int ret; priv->hwbus_ops->lock(priv->hwbus_priv); ret = __cw1200_reg_write(priv, addr, buf, buf_len, 0); priv->hwbus_ops->unlock(priv->hwbus_priv); return ret; } int cw1200_data_read(struct cw1200_common *priv, void *buf, size_t buf_len) { int ret, retry = 1; int buf_id_rx = priv->buf_id_rx; priv->hwbus_ops->lock(priv->hwbus_priv); while (retry <= MAX_RETRY) { ret = __cw1200_reg_read(priv, ST90TDS_IN_OUT_QUEUE_REG_ID, buf, buf_len, buf_id_rx + 1); if (!ret) { buf_id_rx = (buf_id_rx + 1) & 3; priv->buf_id_rx = buf_id_rx; break; } else { retry++; mdelay(1); pr_err("error :[%d]\n", ret); } } priv->hwbus_ops->unlock(priv->hwbus_priv); return ret; } int cw1200_data_write(struct cw1200_common *priv, const void *buf, size_t buf_len) { int ret, retry = 1; int buf_id_tx = priv->buf_id_tx; priv->hwbus_ops->lock(priv->hwbus_priv); while (retry <= MAX_RETRY) { ret = __cw1200_reg_write(priv, ST90TDS_IN_OUT_QUEUE_REG_ID, buf, buf_len, buf_id_tx); if (!ret) { buf_id_tx = (buf_id_tx + 1) & 31; priv->buf_id_tx = buf_id_tx; break; } else { retry++; mdelay(1); pr_err("error :[%d]\n", ret); } } priv->hwbus_ops->unlock(priv->hwbus_priv); return ret; } int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf, size_t buf_len, u32 prefetch, u16 port_addr) { u32 val32 = 0; int i, ret; if ((buf_len / 2) >= 0x1000) { pr_err("Can't read more than 0xfff words.\n"); return -EINVAL; } priv->hwbus_ops->lock(priv->hwbus_priv); /* Write address */ ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr); if (ret < 0) { pr_err("Can't write address register.\n"); goto out; } /* Read CONFIG Register Value - We will read 32 bits */ ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32); if (ret < 0) { pr_err("Can't read config register.\n"); goto out; } /* Set PREFETCH bit */ ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val32 | prefetch); if (ret < 0) { pr_err("Can't write prefetch bit.\n"); goto out; } /* Check for PRE-FETCH bit to be cleared */ for (i = 0; i < 20; i++) { ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32); if (ret < 0) { pr_err("Can't check prefetch bit.\n"); goto out; } if (!(val32 & prefetch)) break; mdelay(i); } if (val32 & prefetch) { pr_err("Prefetch bit is not cleared.\n"); goto out; } /* Read data port */ ret = __cw1200_reg_read(priv, port_addr, buf, buf_len, 0); if (ret < 0) { pr_err("Can't read data port.\n"); goto out; } out: priv->hwbus_ops->unlock(priv->hwbus_priv); return ret; } int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf, size_t buf_len) { int ret; if ((buf_len / 2) >= 0x1000) { pr_err("Can't write more than 0xfff words.\n"); return -EINVAL; } priv->hwbus_ops->lock(priv->hwbus_priv); /* Write address */ ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr); if (ret < 0) { pr_err("Can't write address register.\n"); goto out; } /* Write data port */ ret = __cw1200_reg_write(priv, ST90TDS_SRAM_DPORT_REG_ID, buf, buf_len, 0); if (ret < 0) { pr_err("Can't write data port.\n"); goto out; } out: priv->hwbus_ops->unlock(priv->hwbus_priv); return ret; } int __cw1200_irq_enable(struct cw1200_common *priv, int enable) { u32 val32; u16 val16; int ret; if (HIF_8601_SILICON == priv->hw_type) { ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32); if (ret < 0) { pr_err("Can't read config register.\n"); return ret; } if (enable) val32 |= ST90TDS_CONF_IRQ_RDY_ENABLE; else val32 &= ~ST90TDS_CONF_IRQ_RDY_ENABLE; ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val32); if (ret < 0) { pr_err("Can't write config register.\n"); return ret; } } else { ret = __cw1200_reg_read_16(priv, ST90TDS_CONFIG_REG_ID, &val16); if (ret < 0) { pr_err("Can't read control register.\n"); return ret; } if (enable) val16 |= ST90TDS_CONT_IRQ_RDY_ENABLE; else val16 &= ~ST90TDS_CONT_IRQ_RDY_ENABLE; ret = __cw1200_reg_write_16(priv, ST90TDS_CONFIG_REG_ID, val16); if (ret < 0) { pr_err("Can't write control register.\n"); return ret; } } return 0; } |