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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: "http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Qualcomm CAMSS ISP maintainers: - Robert Foss <robert.foss@linaro.org> description: | The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms properties: compatible: const: qcom,sdm845-camss clocks: minItems: 36 maxItems: 36 clock-names: items: - const: camnoc_axi - const: cpas_ahb - const: cphy_rx_src - const: csi0 - const: csi0_src - const: csi1 - const: csi1_src - const: csi2 - const: csi2_src - const: csiphy0 - const: csiphy0_timer - const: csiphy0_timer_src - const: csiphy1 - const: csiphy1_timer - const: csiphy1_timer_src - const: csiphy2 - const: csiphy2_timer - const: csiphy2_timer_src - const: csiphy3 - const: csiphy3_timer - const: csiphy3_timer_src - const: gcc_camera_ahb - const: gcc_camera_axi - const: slow_ahb_src - const: soc_ahb - const: vfe0_axi - const: vfe0 - const: vfe0_cphy_rx - const: vfe0_src - const: vfe1_axi - const: vfe1 - const: vfe1_cphy_rx - const: vfe1_src - const: vfe_lite - const: vfe_lite_cphy_rx - const: vfe_lite_src interrupts: minItems: 10 maxItems: 10 interrupt-names: items: - const: csid0 - const: csid1 - const: csid2 - const: csiphy0 - const: csiphy1 - const: csiphy2 - const: csiphy3 - const: vfe0 - const: vfe1 - const: vfe_lite iommus: maxItems: 4 power-domains: items: - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. ports: $ref: /schemas/graph.yaml#/properties/ports description: CSI input ports. properties: port@0: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: data-lanes: minItems: 1 maxItems: 4 required: - data-lanes port@1: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: data-lanes: minItems: 1 maxItems: 4 required: - data-lanes port@2: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: data-lanes: minItems: 1 maxItems: 4 required: - data-lanes port@3: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: data-lanes: minItems: 1 maxItems: 4 required: - data-lanes reg: minItems: 10 maxItems: 10 reg-names: items: - const: csid0 - const: csid1 - const: csid2 - const: csiphy0 - const: csiphy1 - const: csiphy2 - const: csiphy3 - const: vfe0 - const: vfe1 - const: vfe_lite vdda-phy-supply: description: Phandle to a regulator supply to PHY core block. vdda-pll-supply: description: Phandle to 1.8V regulator supply to PHY refclk pll block. required: - clock-names - clocks - compatible - interrupt-names - interrupts - iommus - power-domains - reg - reg-names - vdda-phy-supply - vdda-pll-supply additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,camcc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> soc { #address-cells = <2>; #size-cells = <2>; camss: camss@a00000 { compatible = "qcom,sdm845-camss"; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_CPAS_AHB_CLK>, <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY0_CLK>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY1_CLK>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY2_CLK>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY3_CLK>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMERA_AXI_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_CLK>, <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; clock-names = "camnoc_axi", "cpas_ahb", "cphy_rx_src", "csi0", "csi0_src", "csi1", "csi1_src", "csi2", "csi2_src", "csiphy0", "csiphy0_timer", "csiphy0_timer_src", "csiphy1", "csiphy1_timer", "csiphy1_timer_src", "csiphy2", "csiphy2_timer", "csiphy2_timer_src", "csiphy3", "csiphy3_timer", "csiphy3_timer_src", "gcc_camera_ahb", "gcc_camera_axi", "slow_ahb_src", "soc_ahb", "vfe0_axi", "vfe0", "vfe0_cphy_rx", "vfe0_src", "vfe1_axi", "vfe1", "vfe1_cphy_rx", "vfe1_src", "vfe_lite", "vfe_lite_cphy_rx", "vfe_lite_src"; interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "csid0", "csid1", "csid2", "csiphy0", "csiphy1", "csiphy2", "csiphy3", "vfe0", "vfe1", "vfe_lite"; iommus = <&apps_smmu 0x0808 0x0>, <&apps_smmu 0x0810 0x8>, <&apps_smmu 0x0c08 0x0>, <&apps_smmu 0x0c10 0x8>; power-domains = <&clock_camcc IFE_0_GDSC>, <&clock_camcc IFE_1_GDSC>, <&clock_camcc TITAN_TOP_GDSC>; reg = <0 0xacb3000 0 0x1000>, <0 0xacba000 0 0x1000>, <0 0xacc8000 0 0x1000>, <0 0xac65000 0 0x1000>, <0 0xac66000 0 0x1000>, <0 0xac67000 0 0x1000>, <0 0xac68000 0 0x1000>, <0 0xacaf000 0 0x4000>, <0 0xacb6000 0 0x4000>, <0 0xacc4000 0 0x4000>; reg-names = "csid0", "csid1", "csid2", "csiphy0", "csiphy1", "csiphy2", "csiphy3", "vfe0", "vfe1", "vfe_lite"; vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l26a_1p2>; ports { #address-cells = <1>; #size-cells = <0>; }; }; }; |