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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 | // SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for AM6 SoC family in Quad core configuration * * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am65.dtsi" / { cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0: cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; }; cluster1: cluster1 { core0 { cpu = <&cpu2>; }; core1 { cpu = <&cpu3>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0x000>; device_type = "cpu"; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x001>; device_type = "cpu"; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; }; cpu2: cpu@100 { compatible = "arm,cortex-a53"; reg = <0x100>; device_type = "cpu"; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_1>; }; cpu3: cpu@101 { compatible = "arm,cortex-a53"; reg = <0x101>; device_type = "cpu"; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_1>; }; }; L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&msmc_l3>; }; L2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&msmc_l3>; }; msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; }; thermal_zones: thermal-zones { #include "k3-am654-industrial-thermal.dtsi" }; }; |