Linux Audio

Check our new training course

Embedded Linux Audio

Check our new training course
with Creative Commons CC-BY-SA
lecture materials

Bootlin logo

Elixir Cross Referencer

Open Menu / tools / perf / pmu-events / arch / x86 / ivytown / floating-point.json
Loading...
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
[
    {
        "BriefDescription": "Cycles with any input/output SSE or FP assist",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0xCA",
        "EventName": "FP_ASSIST.ANY",
        "PublicDescription": "Cycles with any input/output SSE* or FP assists.",
        "SampleAfterValue": "100003",
        "UMask": "0x1e"
    },
    {
        "BriefDescription": "Number of SIMD FP assists due to input values",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xCA",
        "EventName": "FP_ASSIST.SIMD_INPUT",
        "PublicDescription": "Number of SIMD FP assists due to input values.",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of SIMD FP assists due to Output values",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xCA",
        "EventName": "FP_ASSIST.SIMD_OUTPUT",
        "PublicDescription": "Number of SIMD FP assists due to output values.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of X87 assists due to input value.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xCA",
        "EventName": "FP_ASSIST.X87_INPUT",
        "PublicDescription": "Number of X87 FP assists due to input values.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of X87 assists due to output value.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xCA",
        "EventName": "FP_ASSIST.X87_OUTPUT",
        "PublicDescription": "Number of X87 FP assists due to output values.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x10",
        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
        "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x10",
        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
        "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x10",
        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
        "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
        "SampleAfterValue": "2000003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x10",
        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
        "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x10",
        "EventName": "FP_COMP_OPS_EXE.X87",
        "PublicDescription": "Counts number of X87 uops executed.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x58",
        "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x58",
        "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC1",
        "EventName": "OTHER_ASSISTS.AVX_STORE",
        "PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC1",
        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC1",
        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x11",
        "EventName": "SIMD_FP_256.PACKED_DOUBLE",
        "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x11",
        "EventName": "SIMD_FP_256.PACKED_SINGLE",
        "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    }
]