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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI SoC Ethernet Switch Controller (CPSW) maintainers: - Grygorii Strashko <grygorii.strashko@ti.com> - Sekhar Nori <nsekhar@ti.com> description: The 3-port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch. It provides the gigabit media independent interface (GMII),reduced gigabit media independent interface (RGMII), reduced media independent interface (RMII), the management data input output (MDIO) for physical layer device (PHY) management. properties: compatible: oneOf: - const: ti,cpsw-switch - items: - const: ti,am335x-cpsw-switch - const: ti,cpsw-switch - items: - const: ti,am4372-cpsw-switch - const: ti,cpsw-switch - items: - const: ti,dra7-cpsw-switch - const: ti,cpsw-switch reg: maxItems: 1 description: The physical base address and size of full the CPSW module IO range '#address-cells': const: 1 '#size-cells': const: 1 ranges: true clocks: maxItems: 1 description: CPSW functional clock clock-names: items: - const: fck interrupts: items: - description: RX_THRESH interrupt - description: RX interrupt - description: TX interrupt - description: MISC interrupt interrupt-names: items: - const: "rx_thresh" - const: "rx" - const: "tx" - const: "misc" pinctrl-names: true syscon: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the system control device node which provides access to efuse IO range with MAC addresses ethernet-ports: type: object additionalProperties: false properties: '#address-cells': const: 1 '#size-cells': const: 0 patternProperties: "^port@[0-9]+$": type: object description: CPSW external ports $ref: ethernet-controller.yaml# unevaluatedProperties: false properties: reg: items: - enum: [1, 2] description: CPSW port number phys: maxItems: 1 description: phandle on phy-gmii-sel PHY label: description: label associated with this port ti,dual-emac-pvid: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 1024 description: Specifies default PORT VID to be used to segregate ports. Default value - CPSW port number. required: - reg - phys cpts: type: object unevaluatedProperties: false description: The Common Platform Time Sync (CPTS) module properties: clocks: maxItems: 1 description: CPTS reference clock clock-names: items: - const: cpts cpts_clock_mult: $ref: /schemas/types.yaml#/definitions/uint32 description: Numerator to convert input clock ticks into ns cpts_clock_shift: $ref: /schemas/types.yaml#/definitions/uint32 description: Denominator to convert input clock ticks into ns. Mult and shift will be calculated basing on CPTS rftclk frequency if both cpts_clock_shift and cpts_clock_mult properties are not provided. required: - clocks - clock-names patternProperties: "^mdio@": type: object description: CPSW MDIO bus. $ref: "ti,davinci-mdio.yaml#" required: - compatible - reg - ranges - clocks - clock-names - interrupts - interrupt-names - '#address-cells' - '#size-cells' additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/dra7.h> mac_sw: switch@0 { compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; reg = <0x0 0x4000>; ranges = <0 0 0x4000>; clocks = <&gmac_main_clk>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; syscon = <&scm_conf>; interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "rx_thresh", "rx", "tx", "misc"; ethernet-ports { #address-cells = <1>; #size-cells = <0>; cpsw_port1: port@1 { reg = <1>; label = "port1"; mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 1>; phy-handle = <ðphy0_sw>; phy-mode = "rgmii"; ti,dual-emac-pvid = <1>; }; cpsw_port2: port@2 { reg = <2>; label = "wan"; mac-address = [ 00 00 00 00 00 00 ]; phys = <&phy_gmii_sel 2>; phy-handle = <ðphy1_sw>; phy-mode = "rgmii"; ti,dual-emac-pvid = <2>; }; }; davinci_mdio_sw: mdio@1000 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; reg = <0x1000 0x100>; clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; ethphy0_sw: ethernet-phy@0 { reg = <0>; }; ethphy1_sw: ethernet-phy@1 { reg = <1>; }; }; cpts { clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; clock-names = "cpts"; }; }; |