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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Ptrace test for VMX/VSX registers in the TM context * * Copyright (C) 2015 Anshuman Khandual, IBM Corporation. */ #include "ptrace.h" #include "tm.h" #include "ptrace-vsx.h" int shm_id; unsigned long *cptr, *pptr; unsigned long fp_load[VEC_MAX]; unsigned long fp_store[VEC_MAX]; unsigned long fp_load_ckpt[VEC_MAX]; unsigned long fp_load_ckpt_new[VEC_MAX]; __attribute__((used)) void load_vsx(void) { loadvsx(fp_load, 0); } __attribute__((used)) void load_vsx_ckpt(void) { loadvsx(fp_load_ckpt, 0); } void tm_vsx(void) { unsigned long result, texasr; int ret; cptr = (unsigned long *)shmat(shm_id, NULL, 0); trans: cptr[1] = 0; asm __volatile__( "bl load_vsx_ckpt;" "1: ;" "tbegin.;" "beq 2f;" "bl load_vsx;" "tsuspend.;" "li 7, 1;" "stw 7, 0(%[cptr1]);" "tresume.;" "b .;" "tend.;" "li 0, 0;" "ori %[res], 0, 0;" "b 3f;" "2: ;" "li 0, 1;" "ori %[res], 0, 0;" "mfspr %[texasr], %[sprn_texasr];" "3: ;" : [res] "=r" (result), [texasr] "=r" (texasr) : [sprn_texasr] "i" (SPRN_TEXASR), [cptr1] "b" (&cptr[1]) : "memory", "r0", "r3", "r4", "r7", "r8", "r9", "r10", "r11", "lr" ); if (result) { if (!cptr[0]) goto trans; shmdt((void *)cptr); storevsx(fp_store, 0); ret = compare_vsx_vmx(fp_store, fp_load_ckpt_new); if (ret) exit(1); exit(0); } shmdt((void *)cptr); exit(1); } int trace_tm_vsx(pid_t child) { unsigned long vsx[VSX_MAX]; unsigned long vmx[VMX_MAX + 2][2]; FAIL_IF(start_trace(child)); FAIL_IF(show_vsx(child, vsx)); FAIL_IF(validate_vsx(vsx, fp_load)); FAIL_IF(show_vmx(child, vmx)); FAIL_IF(validate_vmx(vmx, fp_load)); FAIL_IF(show_vsx_ckpt(child, vsx)); FAIL_IF(validate_vsx(vsx, fp_load_ckpt)); FAIL_IF(show_vmx_ckpt(child, vmx)); FAIL_IF(validate_vmx(vmx, fp_load_ckpt)); memset(vsx, 0, sizeof(vsx)); memset(vmx, 0, sizeof(vmx)); load_vsx_vmx(fp_load_ckpt_new, vsx, vmx); FAIL_IF(write_vsx_ckpt(child, vsx)); FAIL_IF(write_vmx_ckpt(child, vmx)); pptr[0] = 1; FAIL_IF(stop_trace(child)); return TEST_PASS; } int ptrace_tm_vsx(void) { pid_t pid; int ret, status, i; SKIP_IF(!have_htm()); SKIP_IF(htm_is_synthetic()); shm_id = shmget(IPC_PRIVATE, sizeof(int) * 2, 0777|IPC_CREAT); for (i = 0; i < 128; i++) { fp_load[i] = 1 + rand(); fp_load_ckpt[i] = 1 + 2 * rand(); fp_load_ckpt_new[i] = 1 + 3 * rand(); } pid = fork(); if (pid < 0) { perror("fork() failed"); return TEST_FAIL; } if (pid == 0) tm_vsx(); if (pid) { pptr = (unsigned long *)shmat(shm_id, NULL, 0); while (!pptr[1]) asm volatile("" : : : "memory"); ret = trace_tm_vsx(pid); if (ret) { kill(pid, SIGKILL); shmdt((void *)pptr); shmctl(shm_id, IPC_RMID, NULL); return TEST_FAIL; } shmdt((void *)pptr); ret = wait(&status); shmctl(shm_id, IPC_RMID, NULL); if (ret != pid) { printf("Child's exit status not captured\n"); return TEST_FAIL; } return (WIFEXITED(status) && WEXITSTATUS(status)) ? TEST_FAIL : TEST_PASS; } return TEST_PASS; } int main(int argc, char *argv[]) { return test_harness(ptrace_tm_vsx, "ptrace_tm_vsx"); } |