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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 | // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2002 ARM Ltd. * All Rights Reserved * Copyright (c) 2010, Code Aurora Forum. All rights reserved. * Copyright (c) 2014 The Linux Foundation. All rights reserved. */ #include <linux/init.h> #include <linux/errno.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/smp.h> #include <linux/io.h> #include <linux/qcom_scm.h> #include <asm/smp_plat.h> #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0 #define SCSS_CPU1CORE_RESET 0x2d80 #define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64 #define APCS_CPU_PWR_CTL 0x04 #define PLL_CLAMP BIT(8) #define CORE_PWRD_UP BIT(7) #define COREPOR_RST BIT(5) #define CORE_RST BIT(4) #define L2DT_SLP BIT(3) #define CORE_MEM_CLAMP BIT(1) #define CLAMP BIT(0) #define APC_PWR_GATE_CTL 0x14 #define BHS_CNT_SHIFT 24 #define LDO_PWR_DWN_SHIFT 16 #define LDO_BYP_SHIFT 8 #define BHS_SEG_SHIFT 1 #define BHS_EN BIT(0) #define APCS_SAW2_VCTL 0x14 #define APCS_SAW2_2_VCTL 0x1c extern void secondary_startup_arm(void); #ifdef CONFIG_HOTPLUG_CPU static void qcom_cpu_die(unsigned int cpu) { wfi(); } #endif static int scss_release_secondary(unsigned int cpu) { struct device_node *node; void __iomem *base; node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); if (!node) { pr_err("%s: can't find node\n", __func__); return -ENXIO; } base = of_iomap(node, 0); of_node_put(node); if (!base) return -ENOMEM; writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); writel_relaxed(0, base + SCSS_CPU1CORE_RESET); writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); mb(); iounmap(base); return 0; } static int cortex_a7_release_secondary(unsigned int cpu) { int ret = 0; void __iomem *reg; struct device_node *cpu_node, *acc_node; u32 reg_val; cpu_node = of_get_cpu_node(cpu, NULL); if (!cpu_node) return -ENODEV; acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); if (!acc_node) { ret = -ENODEV; goto out_acc; } reg = of_iomap(acc_node, 0); if (!reg) { ret = -ENOMEM; goto out_acc_map; } /* Put the CPU into reset. */ reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; writel(reg_val, reg + APCS_CPU_PWR_CTL); /* Turn on the BHS and set the BHS_CNT to 16 XO clock cycles */ writel(BHS_EN | (0x10 << BHS_CNT_SHIFT), reg + APC_PWR_GATE_CTL); /* Wait for the BHS to settle */ udelay(2); reg_val &= ~CORE_MEM_CLAMP; writel(reg_val, reg + APCS_CPU_PWR_CTL); reg_val |= L2DT_SLP; writel(reg_val, reg + APCS_CPU_PWR_CTL); udelay(2); reg_val = (reg_val | BIT(17)) & ~CLAMP; writel(reg_val, reg + APCS_CPU_PWR_CTL); udelay(2); /* Release CPU out of reset and bring it to life. */ reg_val &= ~(CORE_RST | COREPOR_RST); writel(reg_val, reg + APCS_CPU_PWR_CTL); reg_val |= CORE_PWRD_UP; writel(reg_val, reg + APCS_CPU_PWR_CTL); iounmap(reg); out_acc_map: of_node_put(acc_node); out_acc: of_node_put(cpu_node); return ret; } static int kpssv1_release_secondary(unsigned int cpu) { int ret = 0; void __iomem *reg, *saw_reg; struct device_node *cpu_node, *acc_node, *saw_node; u32 val; cpu_node = of_get_cpu_node(cpu, NULL); if (!cpu_node) return -ENODEV; acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); if (!acc_node) { ret = -ENODEV; goto out_acc; } saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); if (!saw_node) { ret = -ENODEV; goto out_saw; } reg = of_iomap(acc_node, 0); if (!reg) { ret = -ENOMEM; goto out_acc_map; } saw_reg = of_iomap(saw_node, 0); if (!saw_reg) { ret = -ENOMEM; goto out_saw_map; } /* Turn on CPU rail */ writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); mb(); udelay(512); /* Krait bring-up sequence */ val = PLL_CLAMP | L2DT_SLP | CLAMP; writel_relaxed(val, reg + APCS_CPU_PWR_CTL); val &= ~L2DT_SLP; writel_relaxed(val, reg + APCS_CPU_PWR_CTL); mb(); ndelay(300); val |= COREPOR_RST; writel_relaxed(val, reg + APCS_CPU_PWR_CTL); mb(); udelay(2); val &= ~CLAMP; writel_relaxed(val, reg + APCS_CPU_PWR_CTL); mb(); udelay(2); val &= ~COREPOR_RST; writel_relaxed(val, reg + APCS_CPU_PWR_CTL); mb(); udelay(100); val |= CORE_PWRD_UP; writel_relaxed(val, reg + APCS_CPU_PWR_CTL); mb(); iounmap(saw_reg); out_saw_map: iounmap(reg); out_acc_map: of_node_put(saw_node); out_saw: of_node_put(acc_node); out_acc: of_node_put(cpu_node); return ret; } static int kpssv2_release_secondary(unsigned int cpu) { void __iomem *reg; struct device_node *cpu_node, *l2_node, *acc_node, *saw_node; void __iomem *l2_saw_base; unsigned reg_val; int ret; cpu_node = of_get_cpu_node(cpu, NULL); if (!cpu_node) return -ENODEV; acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); if (!acc_node) { ret = -ENODEV; goto out_acc; } l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0); if (!l2_node) { ret = -ENODEV; goto out_l2; } saw_node = of_parse_phandle(l2_node, "qcom,saw", 0); if (!saw_node) { ret = -ENODEV; goto out_saw; } reg = of_iomap(acc_node, 0); if (!reg) { ret = -ENOMEM; goto out_map; } l2_saw_base = of_iomap(saw_node, 0); if (!l2_saw_base) { ret = -ENOMEM; goto out_saw_map; } /* Turn on the BHS, turn off LDO Bypass and power down LDO */ reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN; writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); mb(); /* wait for the BHS to settle */ udelay(1); /* Turn on BHS segments */ reg_val |= 0x3f << BHS_SEG_SHIFT; writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); mb(); /* wait for the BHS to settle */ udelay(1); /* Finally turn on the bypass so that BHS supplies power */ reg_val |= 0x3f << LDO_BYP_SHIFT; writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); /* enable max phases */ writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL); mb(); udelay(50); reg_val = COREPOR_RST | CLAMP; writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); mb(); udelay(2); reg_val &= ~CLAMP; writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); mb(); udelay(2); reg_val &= ~COREPOR_RST; writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); mb(); reg_val |= CORE_PWRD_UP; writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); mb(); ret = 0; iounmap(l2_saw_base); out_saw_map: iounmap(reg); out_map: of_node_put(saw_node); out_saw: of_node_put(l2_node); out_l2: of_node_put(acc_node); out_acc: of_node_put(cpu_node); return ret; } static DEFINE_PER_CPU(int, cold_boot_done); static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int)) { int ret = 0; if (!per_cpu(cold_boot_done, cpu)) { ret = func(cpu); if (!ret) per_cpu(cold_boot_done, cpu) = true; } /* * Send the secondary CPU a soft interrupt, thereby causing * the boot monitor to read the system wide flags register, * and branch to the address found there. */ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); return ret; } static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle) { return qcom_boot_secondary(cpu, scss_release_secondary); } static int cortex_a7_boot_secondary(unsigned int cpu, struct task_struct *idle) { return qcom_boot_secondary(cpu, cortex_a7_release_secondary); } static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle) { return qcom_boot_secondary(cpu, kpssv1_release_secondary); } static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle) { return qcom_boot_secondary(cpu, kpssv2_release_secondary); } static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) { int cpu; if (qcom_scm_set_cold_boot_addr(secondary_startup_arm)) { for_each_present_cpu(cpu) { if (cpu == smp_processor_id()) continue; set_cpu_present(cpu, false); } pr_warn("Failed to set CPU boot address, disabling SMP\n"); } } static const struct smp_operations smp_msm8660_ops __initconst = { .smp_prepare_cpus = qcom_smp_prepare_cpus, .smp_boot_secondary = msm8660_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = qcom_cpu_die, #endif }; CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops); static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = { .smp_prepare_cpus = qcom_smp_prepare_cpus, .smp_boot_secondary = cortex_a7_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = qcom_cpu_die, #endif }; CPU_METHOD_OF_DECLARE(qcom_smp_msm8226, "qcom,msm8226-smp", &qcom_smp_cortex_a7_ops); CPU_METHOD_OF_DECLARE(qcom_smp_msm8909, "qcom,msm8909-smp", &qcom_smp_cortex_a7_ops); CPU_METHOD_OF_DECLARE(qcom_smp_msm8916, "qcom,msm8916-smp", &qcom_smp_cortex_a7_ops); static const struct smp_operations qcom_smp_kpssv1_ops __initconst = { .smp_prepare_cpus = qcom_smp_prepare_cpus, .smp_boot_secondary = kpssv1_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = qcom_cpu_die, #endif }; CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops); static const struct smp_operations qcom_smp_kpssv2_ops __initconst = { .smp_prepare_cpus = qcom_smp_prepare_cpus, .smp_boot_secondary = kpssv2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = qcom_cpu_die, #endif }; CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops); |