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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 | /* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DMA_MACRO_MASKS_H_ #define ASIC_REG_DMA_MACRO_MASKS_H_ /* ***************************************** * DMA_MACRO (Prototype: DMA_MACRO) ***************************************** */ /* DMA_MACRO_LBW_RANGE_HIT_BLOCK */ #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF /* DMA_MACRO_LBW_RANGE_MASK */ #define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0 #define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF /* DMA_MACRO_LBW_RANGE_BASE */ #define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0 #define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF /* DMA_MACRO_HBW_RANGE_HIT_BLOCK */ #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF /* DMA_MACRO_HBW_RANGE_MASK_49_32 */ #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF /* DMA_MACRO_HBW_RANGE_MASK_31_0 */ #define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK 0xFFFFFFFF /* DMA_MACRO_HBW_RANGE_BASE_49_32 */ #define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK 0x3FFFF /* DMA_MACRO_HBW_RANGE_BASE_31_0 */ #define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK 0xFFFFFFFF /* DMA_MACRO_WRITE_EN */ #define DMA_MACRO_WRITE_EN_R_SHIFT 0 #define DMA_MACRO_WRITE_EN_R_MASK 0x1 /* DMA_MACRO_WRITE_CREDIT */ #define DMA_MACRO_WRITE_CREDIT_R_SHIFT 0 #define DMA_MACRO_WRITE_CREDIT_R_MASK 0x3FF /* DMA_MACRO_READ_EN */ #define DMA_MACRO_READ_EN_R_SHIFT 0 #define DMA_MACRO_READ_EN_R_MASK 0x1 /* DMA_MACRO_READ_CREDIT */ #define DMA_MACRO_READ_CREDIT_R_SHIFT 0 #define DMA_MACRO_READ_CREDIT_R_MASK 0x3FF /* DMA_MACRO_SRAM_BUSY */ /* DMA_MACRO_RAZWI_LBW_WT_VLD */ #define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_LBW_WT_ID */ #define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK 0x7FFF /* DMA_MACRO_RAZWI_LBW_RD_VLD */ #define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_LBW_RD_ID */ #define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK 0x7FFF /* DMA_MACRO_RAZWI_HBW_WT_VLD */ #define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_HBW_WT_ID */ #define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK 0x1FFFFFFF /* DMA_MACRO_RAZWI_HBW_RD_VLD */ #define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_HBW_RD_ID */ #define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK 0x1FFFFFFF #endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */ |