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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 | /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_SPINLOCK_H #define _ALPHA_SPINLOCK_H #include <linux/kernel.h> #include <asm/current.h> #include <asm/barrier.h> #include <asm/processor.h> /* * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. * * We make no fairness assumptions. They have a cost. */ #define arch_spin_is_locked(x) ((x)->lock != 0) static inline int arch_spin_value_unlocked(arch_spinlock_t lock) { return lock.lock == 0; } static inline void arch_spin_unlock(arch_spinlock_t * lock) { mb(); lock->lock = 0; } static inline void arch_spin_lock(arch_spinlock_t * lock) { long tmp; __asm__ __volatile__( "1: ldl_l %0,%1\n" " bne %0,2f\n" " lda %0,1\n" " stl_c %0,%1\n" " beq %0,2f\n" " mb\n" ".subsection 2\n" "2: ldl %0,%1\n" " bne %0,2b\n" " br 1b\n" ".previous" : "=&r" (tmp), "=m" (lock->lock) : "m"(lock->lock) : "memory"); } static inline int arch_spin_trylock(arch_spinlock_t *lock) { return !test_and_set_bit(0, &lock->lock); } /***********************************************************/ static inline void arch_read_lock(arch_rwlock_t *lock) { long regx; __asm__ __volatile__( "1: ldl_l %1,%0\n" " blbs %1,6f\n" " subl %1,2,%1\n" " stl_c %1,%0\n" " beq %1,6f\n" " mb\n" ".subsection 2\n" "6: ldl %1,%0\n" " blbs %1,6b\n" " br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx) : "m" (*lock) : "memory"); } static inline void arch_write_lock(arch_rwlock_t *lock) { long regx; __asm__ __volatile__( "1: ldl_l %1,%0\n" " bne %1,6f\n" " lda %1,1\n" " stl_c %1,%0\n" " beq %1,6f\n" " mb\n" ".subsection 2\n" "6: ldl %1,%0\n" " bne %1,6b\n" " br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx) : "m" (*lock) : "memory"); } static inline int arch_read_trylock(arch_rwlock_t * lock) { long regx; int success; __asm__ __volatile__( "1: ldl_l %1,%0\n" " lda %2,0\n" " blbs %1,2f\n" " subl %1,2,%2\n" " stl_c %2,%0\n" " beq %2,6f\n" "2: mb\n" ".subsection 2\n" "6: br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx), "=&r" (success) : "m" (*lock) : "memory"); return success; } static inline int arch_write_trylock(arch_rwlock_t * lock) { long regx; int success; __asm__ __volatile__( "1: ldl_l %1,%0\n" " lda %2,0\n" " bne %1,2f\n" " lda %2,1\n" " stl_c %2,%0\n" " beq %2,6f\n" "2: mb\n" ".subsection 2\n" "6: br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx), "=&r" (success) : "m" (*lock) : "memory"); return success; } static inline void arch_read_unlock(arch_rwlock_t * lock) { long regx; __asm__ __volatile__( " mb\n" "1: ldl_l %1,%0\n" " addl %1,2,%1\n" " stl_c %1,%0\n" " beq %1,6f\n" ".subsection 2\n" "6: br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx) : "m" (*lock) : "memory"); } static inline void arch_write_unlock(arch_rwlock_t * lock) { mb(); lock->lock = 0; } #endif /* _ALPHA_SPINLOCK_H */ |