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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 | /* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_IC_PLL_REGS_H_ #define ASIC_REG_IC_PLL_REGS_H_ /* ***************************************** * IC_PLL (Prototype: PLL) ***************************************** */ #define mmIC_PLL_NR 0x4A3100 #define mmIC_PLL_NF 0x4A3104 #define mmIC_PLL_OD 0x4A3108 #define mmIC_PLL_NB 0x4A310C #define mmIC_PLL_CFG 0x4A3110 #define mmIC_PLL_LOSE_MASK 0x4A3120 #define mmIC_PLL_LOCK_INTR 0x4A3128 #define mmIC_PLL_LOCK_BYPASS 0x4A312C #define mmIC_PLL_DATA_CHNG 0x4A3130 #define mmIC_PLL_RST 0x4A3134 #define mmIC_PLL_SLIP_WD_CNTR 0x4A3150 #define mmIC_PLL_DIV_FACTOR_0 0x4A3200 #define mmIC_PLL_DIV_FACTOR_1 0x4A3204 #define mmIC_PLL_DIV_FACTOR_2 0x4A3208 #define mmIC_PLL_DIV_FACTOR_3 0x4A320C #define mmIC_PLL_DIV_FACTOR_CMD_0 0x4A3220 #define mmIC_PLL_DIV_FACTOR_CMD_1 0x4A3224 #define mmIC_PLL_DIV_FACTOR_CMD_2 0x4A3228 #define mmIC_PLL_DIV_FACTOR_CMD_3 0x4A322C #define mmIC_PLL_DIV_SEL_0 0x4A3280 #define mmIC_PLL_DIV_SEL_1 0x4A3284 #define mmIC_PLL_DIV_SEL_2 0x4A3288 #define mmIC_PLL_DIV_SEL_3 0x4A328C #define mmIC_PLL_DIV_EN_0 0x4A32A0 #define mmIC_PLL_DIV_EN_1 0x4A32A4 #define mmIC_PLL_DIV_EN_2 0x4A32A8 #define mmIC_PLL_DIV_EN_3 0x4A32AC #define mmIC_PLL_DIV_FACTOR_BUSY_0 0x4A32C0 #define mmIC_PLL_DIV_FACTOR_BUSY_1 0x4A32C4 #define mmIC_PLL_DIV_FACTOR_BUSY_2 0x4A32C8 #define mmIC_PLL_DIV_FACTOR_BUSY_3 0x4A32CC #define mmIC_PLL_CLK_GATER 0x4A3300 #define mmIC_PLL_CLK_RLX_0 0x4A3310 #define mmIC_PLL_CLK_RLX_1 0x4A3314 #define mmIC_PLL_CLK_RLX_2 0x4A3318 #define mmIC_PLL_CLK_RLX_3 0x4A331C #define mmIC_PLL_REF_CNTR_PERIOD 0x4A3400 #define mmIC_PLL_REF_LOW_THRESHOLD 0x4A3410 #define mmIC_PLL_REF_HIGH_THRESHOLD 0x4A3420 #define mmIC_PLL_PLL_NOT_STABLE 0x4A3430 #define mmIC_PLL_FREQ_CALC_EN 0x4A3440 #endif /* ASIC_REG_IC_PLL_REGS_H_ */ |