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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Performance counter support for e6500 family processors. * * Author: Priyanka Jain, Priyanka.Jain@freescale.com * Based on e500-pmu.c * Copyright 2013 Freescale Semiconductor, Inc. * Copyright 2008-2009 Paul Mackerras, IBM Corporation. */ #include <linux/string.h> #include <linux/perf_event.h> #include <asm/reg.h> #include <asm/cputable.h> /* * Map of generic hardware event types to hardware events * Zero if unsupported */ static int e6500_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES] = 1, [PERF_COUNT_HW_INSTRUCTIONS] = 2, [PERF_COUNT_HW_CACHE_MISSES] = 221, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12, [PERF_COUNT_HW_BRANCH_MISSES] = 15, }; #define C(x) PERF_COUNT_HW_CACHE_##x /* * Table of generalized cache-related events. * 0 means not supported, -1 means nonsensical, other values * are event codes. */ static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(L1D)] = { /*RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 27, 222 }, [C(OP_WRITE)] = { 28, 223 }, [C(OP_PREFETCH)] = { 29, 0 }, }, [C(L1I)] = { /*RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 2, 254 }, [C(OP_WRITE)] = { -1, -1 }, [C(OP_PREFETCH)] = { 37, 0 }, }, /* * Assuming LL means L2, it's not a good match for this model. * It does not have separate read/write events (but it does have * separate instruction/data events). */ [C(LL)] = { /*RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 0, 0 }, [C(OP_WRITE)] = { 0, 0 }, [C(OP_PREFETCH)] = { 0, 0 }, }, /* * There are data/instruction MMU misses, but that's a miss on * the chip's internal level-one TLB which is probably not * what the user wants. Instead, unified level-two TLB misses * are reported here. */ [C(DTLB)] = { /*RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 26, 66 }, [C(OP_WRITE)] = { -1, -1 }, [C(OP_PREFETCH)] = { -1, -1 }, }, [C(BPU)] = { /*RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 12, 15 }, [C(OP_WRITE)] = { -1, -1 }, [C(OP_PREFETCH)] = { -1, -1 }, }, [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { -1, -1 }, [C(OP_WRITE)] = { -1, -1 }, [C(OP_PREFETCH)] = { -1, -1 }, }, }; static int num_events = 512; /* Upper half of event id is PMLCb, for threshold events */ static u64 e6500_xlate_event(u64 event_id) { u32 event_low = (u32)event_id; if (event_low >= num_events || (event_id & (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH))) return 0; return FSL_EMB_EVENT_VALID; } static struct fsl_emb_pmu e6500_pmu = { .name = "e6500 family", .n_counter = 6, .n_restricted = 0, .xlate_event = e6500_xlate_event, .n_generic = ARRAY_SIZE(e6500_generic_events), .generic_events = e6500_generic_events, .cache_events = &e6500_cache_events, }; static int init_e6500_pmu(void) { unsigned int pvr = mfspr(SPRN_PVR); if (PVR_VER(pvr) != PVR_VER_E6500) return -ENODEV; return register_fsl_emb_pmu(&e6500_pmu); } early_initcall(init_e6500_pmu); |