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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright 2020 Linaro Ltd. %YAML 1.2 --- $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Thermal idle cooling device binding maintainers: - Daniel Lezcano <daniel.lezcano@linaro.org> description: | The thermal idle cooling device allows the system to passively mitigate the temperature on the device by injecting idle cycles, forcing it to cool down. This binding describes the thermal idle node. properties: $nodename: const: thermal-idle description: | A thermal-idle node describes the idle cooling device properties to cool down efficiently the attached thermal zone. '#cooling-cells': const: 2 description: | Must be 2, in order to specify minimum and maximum cooling state used in the cooling-maps reference. The first cell is the minimum cooling state and the second cell is the maximum cooling state requested. duration-us: description: | The idle duration in microsecond the device should cool down. exit-latency-us: description: | The exit latency constraint in microsecond for the injected idle state for the device. It is the latency constraint to apply when selecting an idle state from among all the present ones. required: - '#cooling-cells' additionalProperties: false examples: - | #include <dt-bindings/thermal/thermal.h> // Example: Combining idle cooling device on big CPUs with cpufreq cooling device cpus { #address-cells = <2>; #size-cells = <0>; /* ... */ cpu_b0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <436>; #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>; thermal-idle { #cooling-cells = <2>; duration-us = <10000>; exit-latency-us = <500>; }; }; cpu_b1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <436>; #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>; thermal-idle { #cooling-cells = <2>; duration-us = <10000>; exit-latency-us = <500>; }; }; /* ... */ }; /* ... */ thermal_zones { cpu_thermal: cpu { polling-delay-passive = <100>; polling-delay = <1000>; /* ... */ trips { cpu_alert0: cpu_alert0 { temperature = <65000>; hysteresis = <2000>; type = "passive"; }; cpu_alert1: cpu_alert1 { temperature = <70000>; hysteresis = <2000>; type = "passive"; }; cpu_alert2: cpu_alert2 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; cpu_crit: cpu_crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_alert1>; cooling-device = <&{/cpus/cpu@100/thermal-idle} 0 15 >, <&{/cpus/cpu@101/thermal-idle} 0 15>; }; map1 { trip = <&cpu_alert2>; cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; |