Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/mux/reg-mux.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic register bitfield-based multiplexer controller bindings maintainers: - Peter Rosin <peda@axentia.se> description: |+ Define register bitfields to be used to control multiplexers. The parent device tree node must be a device node to provide register r/w access. properties: compatible: enum: - reg-mux # parent device of mux controller is not syscon device - mmio-mux # parent device of mux controller is syscon device reg: true '#mux-control-cells': const: 1 mux-reg-masks: $ref: /schemas/types.yaml#/definitions/uint32-matrix items: items: - description: register offset - description: pre-shifted bitfield mask description: Each entry pair describes a single mux control. idle-states: true required: - compatible - mux-reg-masks - '#mux-control-cells' additionalProperties: false examples: - | /* The parent device of mux controller is not a syscon device. */ #include <dt-bindings/mux/mux.h> mux-controller { compatible = "reg-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ }; mdio-mux-1 { compatible = "mdio-mux-multiplexer"; mux-controls = <&mux1 0>; mdio-parent-bus = <&emdio1>; #address-cells = <1>; #size-cells = <0>; mdio@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; mdio@8 { reg = <0x8>; #address-cells = <1>; #size-cells = <0>; }; }; mdio-mux-2 { compatible = "mdio-mux-multiplexer"; mux-controls = <&mux1 1>; mdio-parent-bus = <&emdio2>; #address-cells = <1>; #size-cells = <0>; mdio@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; mdio@1 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; }; - | /* The parent device of mux controller is syscon device. */ #include <dt-bindings/mux/mux.h> syscon@1000 { reg = <0x1000 0x100>; mux2: mux-controller { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */ <0x3 0x40>; /* 1: reg 0x3, bit 6 */ idle-states = <MUX_IDLE_AS_IS>, <0>; }; }; video-mux { compatible = "video-mux"; mux-controls = <&mux2 0>; #address-cells = <1>; #size-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; /* inputs 0..3 */ port@0 { reg = <0>; }; port@1 { reg = <1>; }; port@2 { reg = <2>; }; port@3 { reg = <3>; }; /* output */ port@4 { reg = <4>; }; }; }; ... |