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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 | // SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for AM62A SoC Family Main Domain peripherals * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { oc_sram: sram@70000000 { compatible = "mmio-sram"; reg = <0x00 0x70000000 0x00 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x70000000 0x10000>; }; gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01880000 0x00 0xc0000>, /* GICR */ <0x00 0x01880000 0x00 0xc0000>, /* GICR */ <0x01 0x00000000 0x00 0x2000>, /* GICC */ <0x01 0x00010000 0x00 0x1000>, /* GICH */ <0x01 0x00020000 0x00 0x2000>; /* GICV */ #address-cells = <2>; #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; /* * vcpumntirq: * virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; gic_its: msi-controller@1820000 { compatible = "arm,gic-v3-its"; reg = <0x00 0x01820000 0x00 0x10000>; socionext,synquacer-pre-its = <0x1000000 0x400000>; msi-controller; #msi-cells = <1>; }; }; main_conf: syscon@100000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x00 0x00100000 0x00 0x20000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; }; dmss: bus@48000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; dma-ranges; ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; ti,sci-dev-id = <25>; secure_proxy_main: mailbox@4d000000 { compatible = "ti,am654-secure-proxy"; reg = <0x00 0x4d000000 0x00 0x80000>, <0x00 0x4a600000 0x00 0x80000>, <0x00 0x4a400000 0x00 0x80000>; reg-names = "target_data", "rt", "scfg"; #mbox-cells = <1>; interrupt-names = "rx_012"; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; }; dmsc: system-controller@44043000 { compatible = "ti,k2g-sci"; reg = <0x00 0x44043000 0x00 0xfe0>; reg-names = "debug_messages"; ti,host-id = <12>; mbox-names = "rx", "tx"; mboxes= <&secure_proxy_main 12>, <&secure_proxy_main 13>; k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; }; }; main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; status = "disabled"; }; main_uart1: serial@2810000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; status = "disabled"; }; main_uart2: serial@2820000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; status = "disabled"; }; main_uart3: serial@2830000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; status = "disabled"; }; main_uart4: serial@2840000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; status = "disabled"; }; main_uart5: serial@2850000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; status = "disabled"; }; main_uart6: serial@2860000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; status = "disabled"; }; main_i2c0: i2c@20000000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; reg = <0x00 0x20000000 0x00 0x100>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; status = "disabled"; }; main_i2c1: i2c@20010000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; reg = <0x00 0x20010000 0x00 0x100>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; status = "disabled"; }; main_i2c2: i2c@20020000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; reg = <0x00 0x20020000 0x00 0x100>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; status = "disabled"; }; main_i2c3: i2c@20030000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; reg = <0x00 0x20030000 0x00 0x100>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <3>; ti,interrupt-ranges = <0 32 16>; status = "disabled"; }; main_gpio0: gpio@600000 { compatible = "ti,am64-gpio", "ti,keystone-gpio"; reg = <0x00 0x00600000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <190>, <191>, <192>, <193>, <194>, <195>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <87>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 77 0>; clock-names = "gpio"; status = "disabled"; }; main_gpio1: gpio@601000 { compatible = "ti,am64-gpio", "ti,keystone-gpio"; reg = <0x00 0x00601000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <180>, <181>, <182>, <183>, <184>, <185>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <88>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 78 0>; clock-names = "gpio"; status = "disabled"; }; sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; ti,clkbuf-sel = <0x7>; bus-width = <4>; no-1-8-v; status = "disabled"; }; }; |