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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 | // SPDX-License-Identifier: GPL-2.0 /* * MFD core driver for Intel Cherrytrail Whiskey Cove PMIC * * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com> * * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: * Copyright (C) 2013-2015 Intel Corporation. All rights reserved. */ #include <linux/acpi.h> #include <linux/delay.h> #include <linux/dmi.h> #include <linux/err.h> #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/mfd/core.h> #include <linux/mfd/intel_soc_pmic.h> #include <linux/regmap.h> /* PMIC device registers */ #define REG_OFFSET_MASK GENMASK(7, 0) #define REG_ADDR_MASK GENMASK(15, 8) #define REG_ADDR_SHIFT 8 #define CHT_WC_IRQLVL1 0x6e02 #define CHT_WC_IRQLVL1_MASK 0x6e0e /* Whiskey Cove PMIC share same ACPI ID between different platforms */ #define CHT_WC_HRV 3 /* Level 1 IRQs (level 2 IRQs are handled in the child device drivers) */ enum { CHT_WC_PWRSRC_IRQ = 0, CHT_WC_THRM_IRQ, CHT_WC_BCU_IRQ, CHT_WC_ADC_IRQ, CHT_WC_EXT_CHGR_IRQ, CHT_WC_GPIO_IRQ, /* There is no irq 6 */ CHT_WC_CRIT_IRQ = 7, }; static const struct resource cht_wc_pwrsrc_resources[] = { DEFINE_RES_IRQ(CHT_WC_PWRSRC_IRQ), }; static const struct resource cht_wc_ext_charger_resources[] = { DEFINE_RES_IRQ(CHT_WC_EXT_CHGR_IRQ), }; static struct mfd_cell cht_wc_dev[] = { { .name = "cht_wcove_pwrsrc", .num_resources = ARRAY_SIZE(cht_wc_pwrsrc_resources), .resources = cht_wc_pwrsrc_resources, }, { .name = "cht_wcove_ext_chgr", .num_resources = ARRAY_SIZE(cht_wc_ext_charger_resources), .resources = cht_wc_ext_charger_resources, }, { .name = "cht_wcove_region", }, { .name = "cht_wcove_leds", }, }; /* * The CHT Whiskey Cove covers multiple I2C addresses, with a 1 Byte * register address space per I2C address, so we use 16 bit register * addresses where the high 8 bits contain the I2C client address. */ static int cht_wc_byte_reg_read(void *context, unsigned int reg, unsigned int *val) { struct i2c_client *client = context; int ret, orig_addr = client->addr; if (!(reg & REG_ADDR_MASK)) { dev_err(&client->dev, "Error I2C address not specified\n"); return -EINVAL; } client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; ret = i2c_smbus_read_byte_data(client, reg & REG_OFFSET_MASK); client->addr = orig_addr; if (ret < 0) return ret; *val = ret; return 0; } static int cht_wc_byte_reg_write(void *context, unsigned int reg, unsigned int val) { struct i2c_client *client = context; int ret, orig_addr = client->addr; if (!(reg & REG_ADDR_MASK)) { dev_err(&client->dev, "Error I2C address not specified\n"); return -EINVAL; } client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; ret = i2c_smbus_write_byte_data(client, reg & REG_OFFSET_MASK, val); client->addr = orig_addr; return ret; } static const struct regmap_config cht_wc_regmap_cfg = { .reg_bits = 16, .val_bits = 8, .reg_write = cht_wc_byte_reg_write, .reg_read = cht_wc_byte_reg_read, }; static const struct regmap_irq cht_wc_regmap_irqs[] = { REGMAP_IRQ_REG(CHT_WC_PWRSRC_IRQ, 0, BIT(CHT_WC_PWRSRC_IRQ)), REGMAP_IRQ_REG(CHT_WC_THRM_IRQ, 0, BIT(CHT_WC_THRM_IRQ)), REGMAP_IRQ_REG(CHT_WC_BCU_IRQ, 0, BIT(CHT_WC_BCU_IRQ)), REGMAP_IRQ_REG(CHT_WC_ADC_IRQ, 0, BIT(CHT_WC_ADC_IRQ)), REGMAP_IRQ_REG(CHT_WC_EXT_CHGR_IRQ, 0, BIT(CHT_WC_EXT_CHGR_IRQ)), REGMAP_IRQ_REG(CHT_WC_GPIO_IRQ, 0, BIT(CHT_WC_GPIO_IRQ)), REGMAP_IRQ_REG(CHT_WC_CRIT_IRQ, 0, BIT(CHT_WC_CRIT_IRQ)), }; static const struct regmap_irq_chip cht_wc_regmap_irq_chip = { .name = "cht_wc_irq_chip", .status_base = CHT_WC_IRQLVL1, .mask_base = CHT_WC_IRQLVL1_MASK, .irqs = cht_wc_regmap_irqs, .num_irqs = ARRAY_SIZE(cht_wc_regmap_irqs), .num_regs = 1, }; static const struct dmi_system_id cht_wc_model_dmi_ids[] = { { /* GPD win / GPD pocket mini laptops */ .driver_data = (void *)(long)INTEL_CHT_WC_GPD_WIN_POCKET, /* * This DMI match may not seem unique, but it is. In the 67000+ * DMI decode dumps from linux-hardware.org only 116 have * board_vendor set to "AMI Corporation" and of those 116 only * the GPD win's and pocket's board_name is "Default string". */ .matches = { DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), DMI_EXACT_MATCH(DMI_BOARD_SERIAL, "Default string"), DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"), }, }, { /* Xiaomi Mi Pad 2 */ .driver_data = (void *)(long)INTEL_CHT_WC_XIAOMI_MIPAD2, .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Xiaomi Inc"), DMI_MATCH(DMI_PRODUCT_NAME, "Mipad2"), }, }, { /* Lenovo Yoga Book X90F / X91F / X91L */ .driver_data = (void *)(long)INTEL_CHT_WC_LENOVO_YOGABOOK1, .matches = { /* Non exact match to match all versions */ DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X9"), }, }, { } }; static int cht_wc_probe(struct i2c_client *client) { struct device *dev = &client->dev; const struct dmi_system_id *id; struct intel_soc_pmic *pmic; acpi_status status; unsigned long long hrv; int ret; status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv); if (ACPI_FAILURE(status)) return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n"); if (hrv != CHT_WC_HRV) return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv); if (client->irq < 0) return dev_err_probe(dev, -EINVAL, "Invalid IRQ\n"); pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); if (!pmic) return -ENOMEM; id = dmi_first_match(cht_wc_model_dmi_ids); if (id) pmic->cht_wc_model = (long)id->driver_data; pmic->irq = client->irq; pmic->dev = dev; i2c_set_clientdata(client, pmic); pmic->regmap = devm_regmap_init(dev, NULL, client, &cht_wc_regmap_cfg); if (IS_ERR(pmic->regmap)) return PTR_ERR(pmic->regmap); ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq, IRQF_ONESHOT | IRQF_SHARED, 0, &cht_wc_regmap_irq_chip, &pmic->irq_chip_data); if (ret) return ret; return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, cht_wc_dev, ARRAY_SIZE(cht_wc_dev), NULL, 0, regmap_irq_get_domain(pmic->irq_chip_data)); } static void cht_wc_shutdown(struct i2c_client *client) { struct intel_soc_pmic *pmic = i2c_get_clientdata(client); disable_irq(pmic->irq); } static int cht_wc_suspend(struct device *dev) { struct intel_soc_pmic *pmic = dev_get_drvdata(dev); disable_irq(pmic->irq); return 0; } static int cht_wc_resume(struct device *dev) { struct intel_soc_pmic *pmic = dev_get_drvdata(dev); enable_irq(pmic->irq); return 0; } static DEFINE_SIMPLE_DEV_PM_OPS(cht_wc_pm_ops, cht_wc_suspend, cht_wc_resume); static const struct i2c_device_id cht_wc_i2c_id[] = { { } }; static const struct acpi_device_id cht_wc_acpi_ids[] = { { "INT34D3", }, { } }; static struct i2c_driver cht_wc_driver = { .driver = { .name = "CHT Whiskey Cove PMIC", .pm = pm_sleep_ptr(&cht_wc_pm_ops), .acpi_match_table = cht_wc_acpi_ids, }, .probe_new = cht_wc_probe, .shutdown = cht_wc_shutdown, .id_table = cht_wc_i2c_id, }; builtin_i2c_driver(cht_wc_driver); |