Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree For AC5. * * Copyright (C) 2021 Marvell * Copyright (C) 2022 Allied Telesis Labs */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { model = "Marvell AC5 SoC"; compatible = "marvell,ac5"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; }; }; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2>; }; l2: l2-cache { compatible = "cache"; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; internal-regs@7f000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; /* 16M internal register @ 0x7f00_0000 */ ranges = <0x0 0x0 0x7f000000 0x1000000>; dma-coherent; uart0: serial@12000 { compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; clocks = <&cnm_clock>; status = "okay"; }; uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; clocks = <&cnm_clock>; status = "disabled"; }; uart2: serial@12200 { compatible = "snps,dw-apb-uart"; reg = <0x12200 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; clocks = <&cnm_clock>; status = "disabled"; }; uart3: serial@12300 { compatible = "snps,dw-apb-uart"; reg = <0x12300 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; clocks = <&cnm_clock>; status = "disabled"; }; mdio: mdio@22004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x22004 0x4>; clocks = <&cnm_clock>; }; i2c0: i2c@11000{ compatible = "marvell,mv78230-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; clocks = <&cnm_clock>; clock-names = "core"; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clock-frequency=<100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c0_pins>; pinctrl-1 = <&i2c0_gpio>; scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; i2c1: i2c@11100{ compatible = "marvell,mv78230-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; clocks = <&cnm_clock>; clock-names = "core"; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clock-frequency=<100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c1_pins>; pinctrl-1 = <&i2c1_gpio>; scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl0 0 0 32>; marvell,pwm-offset = <0x1f0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; }; gpio1: gpio@18140 { reg = <0x18140 0x40>; compatible = "marvell,orion-gpio"; ngpios = <14>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl0 0 32 14>; marvell,pwm-offset = <0x1f0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; }; }; /* * Dedicated section for devices behind 32bit controllers so we * can configure specific DMA mapping for them */ behind-32bit-controller@7f000000 { compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; /* Host phy ram starts at 0x200M */ dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; dma-coherent; eth0: ethernet@20000 { compatible = "marvell,armada-ac5-neta"; reg = <0x0 0x20000 0x0 0x4000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cnm_clock>; phy-mode = "sgmii"; status = "disabled"; }; eth1: ethernet@24000 { compatible = "marvell,armada-ac5-neta"; reg = <0x0 0x24000 0x0 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cnm_clock>; phy-mode = "sgmii"; status = "disabled"; }; usb0: usb@80000 { compatible = "marvell,orion-ehci"; reg = <0x0 0x80000 0x0 0x500>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; usb1: usb@a0000 { compatible = "marvell,orion-ehci"; reg = <0x0 0xa0000 0x0 0x500>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; pinctrl0: pinctrl@80020100 { compatible = "marvell,ac5-pinctrl"; reg = <0 0x80020100 0 0x20>; i2c0_pins: i2c0-pins { marvell,pins = "mpp26", "mpp27"; marvell,function = "i2c0"; }; i2c0_gpio: i2c0-gpio-pins { marvell,pins = "mpp26", "mpp27"; marvell,function = "gpio"; }; i2c1_pins: i2c1-pins { marvell,pins = "mpp20", "mpp21"; marvell,function = "i2c1"; }; i2c1_gpio: i2c1-gpio-pins { marvell,pins = "mpp20", "mpp21"; marvell,function = "i2c1"; }; }; spi0: spi@805a0000 { compatible = "marvell,armada-3700-spi"; reg = <0x0 0x805a0000 0x0 0x50>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <&spi_clock>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; num-cs = <1>; status = "disabled"; }; spi1: spi@805a8000 { compatible = "marvell,armada-3700-spi"; reg = <0x0 0x805a8000 0x0 0x50>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <&spi_clock>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; num-cs = <1>; status = "disabled"; }; gic: interrupt-controller@80600000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ <0x0 0x80660000 0x0 0x40000>; /* GICR */ interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; }; }; clocks { cnm_clock: cnm-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <328000000>; }; spi_clock: spi-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; }; |