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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 | // SPDX-License-Identifier: (GPL-2.0 or MIT) /* * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC * * Copyright (C) 2021 Renesas Electronics Corp. */ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a779f0-sysc.h> / { compatible = "renesas,r8a779f0"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&a55_0>; }; core1 { cpu = <&a55_1>; }; }; cluster1 { core0 { cpu = <&a55_2>; }; core1 { cpu = <&a55_3>; }; }; cluster2 { core0 { cpu = <&a55_4>; }; core1 { cpu = <&a55_5>; }; }; cluster3 { core0 { cpu = <&a55_6>; }; core1 { cpu = <&a55_7>; }; }; }; a55_0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; next-level-cache = <&L3_CA55_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_1: cpu@100 { compatible = "arm,cortex-a55"; reg = <0x100>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; next-level-cache = <&L3_CA55_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_2: cpu@10000 { compatible = "arm,cortex-a55"; reg = <0x10000>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; next-level-cache = <&L3_CA55_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_3: cpu@10100 { compatible = "arm,cortex-a55"; reg = <0x10100>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; next-level-cache = <&L3_CA55_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_4: cpu@20000 { compatible = "arm,cortex-a55"; reg = <0x20000>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; next-level-cache = <&L3_CA55_2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_5: cpu@20100 { compatible = "arm,cortex-a55"; reg = <0x20100>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; next-level-cache = <&L3_CA55_2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_6: cpu@30000 { compatible = "arm,cortex-a55"; reg = <0x30000>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; next-level-cache = <&L3_CA55_3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_7: cpu@30100 { compatible = "arm,cortex-a55"; reg = <0x30100>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; next-level-cache = <&L3_CA55_3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; L3_CA55_0: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A779F0_PD_A2E0D0>; cache-unified; cache-level = <3>; }; L3_CA55_1: cache-controller-1 { compatible = "cache"; power-domains = <&sysc R8A779F0_PD_A2E0D1>; cache-unified; cache-level = <3>; }; L3_CA55_2: cache-controller-2 { compatible = "cache"; power-domains = <&sysc R8A779F0_PD_A2E1D0>; cache-unified; cache-level = <3>; }; L3_CA55_3: cache-controller-3 { compatible = "cache"; power-domains = <&sysc R8A779F0_PD_A2E1D1>; cache-unified; cache-level = <3>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; local-timer-stop; entry-latency-us = <400>; exit-latency-us = <500>; min-residency-us = <4000>; }; }; }; extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; pmu_a55 { compatible = "arm,cortex-a55-pmu"; interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; rwdt: watchdog@e6020000 { compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 907>; status = "disabled"; }; pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779f0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; }; gpio0: gpio@e6050180 { compatible = "renesas,gpio-r8a779f0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6050180 0 0x54>; interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 0 21>; interrupt-controller; #interrupt-cells = <2>; }; gpio1: gpio@e6050980 { compatible = "renesas,gpio-r8a779f0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6050980 0 0x54>; interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 32 25>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@e6051180 { compatible = "renesas,gpio-r8a779f0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6051180 0 0x54>; interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 64 17>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@e6051980 { compatible = "renesas,gpio-r8a779f0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6051980 0 0x54>; interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 96 19>; interrupt-controller; #interrupt-cells = <2>; }; cmt0: timer@e60f0000 { compatible = "renesas,r8a779f0-cmt0", "renesas,rcar-gen4-cmt0"; reg = <0 0xe60f0000 0 0x1004>; interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 910>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 910>; status = "disabled"; }; cmt1: timer@e6130000 { compatible = "renesas,r8a779f0-cmt1", "renesas,rcar-gen4-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 911>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 911>; status = "disabled"; }; cmt2: timer@e6140000 { compatible = "renesas,r8a779f0-cmt1", "renesas,rcar-gen4-cmt1"; reg = <0 0xe6140000 0 0x1004>; interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 912>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 912>; status = "disabled"; }; cmt3: timer@e6148000 { compatible = "renesas,r8a779f0-cmt1", "renesas,rcar-gen4-cmt1"; reg = <0 0xe6148000 0 0x1004>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 913>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 913>; status = "disabled"; }; cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; clocks = <&extal_clk>, <&extalr_clk>; clock-names = "extal", "extalr"; #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779f0-rst"; reg = <0 0xe6160000 0 0x4000>; }; sysc: system-controller@e6180000 { compatible = "renesas,r8a779f0-sysc"; reg = <0 0xe6180000 0 0x4000>; #power-domain-cells = <1>; }; tsc: thermal@e6198000 { compatible = "renesas,r8a779f0-thermal"; /* The 4th sensor is in control domain and not for Linux */ reg = <0 0xe6198000 0 0x200>, <0 0xe61a0000 0 0x200>, <0 0xe61a8000 0 0x200>; clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 919>; #thermal-sensor-cells = <1>; }; tmu0: timer@e61e0000 { compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; reg = <0 0xe61e0000 0 0x30>; interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 713>; status = "disabled"; }; tmu1: timer@e6fc0000 { compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 714>; status = "disabled"; }; tmu2: timer@e6fd0000 { compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 715>; status = "disabled"; }; tmu3: timer@e6fe0000 { compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; reg = <0 0xe6fe0000 0 0x30>; interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 716>; status = "disabled"; }; tmu4: timer@ffc00000 { compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; reg = <0 0xffc00000 0 0x30>; interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 717>; status = "disabled"; }; i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; reg = <0 0xe6500000 0 0x40>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 518>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 518>; dmas = <&dmac0 0x91>, <&dmac0 0x90>, <&dmac1 0x91>, <&dmac1 0x90>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@e6508000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 519>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 519>; dmas = <&dmac0 0x93>, <&dmac0 0x92>, <&dmac1 0x93>, <&dmac1 0x92>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@e6510000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; reg = <0 0xe6510000 0 0x40>; interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 520>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 520>; dmas = <&dmac0 0x95>, <&dmac0 0x94>, <&dmac1 0x95>, <&dmac1 0x94>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@e66d0000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; reg = <0 0xe66d0000 0 0x40>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 521>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 521>; dmas = <&dmac0 0x97>, <&dmac0 0x96>, <&dmac1 0x97>, <&dmac1 0x96>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@e66d8000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; reg = <0 0xe66d8000 0 0x40>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 522>; dmas = <&dmac0 0x99>, <&dmac0 0x98>, <&dmac1 0x99>, <&dmac1 0x98>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c5: i2c@e66e0000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; reg = <0 0xe66e0000 0 0x40>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 523>; dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, <&dmac1 0x9b>, <&dmac1 0x9a>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a779f0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6540000 0 0x60>; interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x31>, <&dmac0 0x30>, <&dmac1 0x31>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 514>; status = "disabled"; }; hscif1: serial@e6550000 { compatible = "renesas,hscif-r8a779f0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 515>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x33>, <&dmac0 0x32>, <&dmac1 0x33>, <&dmac1 0x32>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 515>; status = "disabled"; }; hscif2: serial@e6560000 { compatible = "renesas,hscif-r8a779f0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6560000 0 0x60>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 516>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x35>, <&dmac0 0x34>, <&dmac1 0x35>, <&dmac1 0x34>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 516>; status = "disabled"; }; hscif3: serial@e66a0000 { compatible = "renesas,hscif-r8a779f0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe66a0000 0 0x60>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 517>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x37>, <&dmac0 0x36>, <&dmac1 0x37>, <&dmac1 0x36>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 517>; status = "disabled"; }; ufs: ufs@e6860000 { compatible = "renesas,r8a779f0-ufs"; reg = <0 0xe6860000 0 0x100>; interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; clock-names = "fck", "ref_clk"; freq-table-hz = <200000000 200000000>, <38400000 38400000>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 1514>; status = "disabled"; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x51>, <&dmac0 0x50>, <&dmac1 0x51>, <&dmac1 0x50>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x53>, <&dmac0 0x52>, <&dmac1 0x53>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; }; scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>, <&dmac1 0x57>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 704>; status = "disabled"; }; scif4: serial@e6c40000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 705>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>, <&dmac1 0x59>, <&dmac1 0x58>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 705>; status = "disabled"; }; msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a779f0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6e90000 0 0x0064>; interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 618>; dmas = <&dmac0 0x41>, <&dmac0 0x40>, <&dmac1 0x41>, <&dmac1 0x40>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 618>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof1: spi@e6ea0000 { compatible = "renesas,msiof-r8a779f0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6ea0000 0 0x0064>; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 619>; dmas = <&dmac0 0x43>, <&dmac0 0x42>, <&dmac1 0x43>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 619>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof2: spi@e6c00000 { compatible = "renesas,msiof-r8a779f0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6c00000 0 0x0064>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 620>; dmas = <&dmac0 0x45>, <&dmac0 0x44>, <&dmac1 0x45>, <&dmac1 0x44>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 620>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof3: spi@e6c10000 { compatible = "renesas,msiof-r8a779f0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6c10000 0 0x0064>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; dmas = <&dmac0 0x47>, <&dmac0 0x46>, <&dmac1 0x47>, <&dmac1 0x46>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 621>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; dmac0: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779f0", "renesas,rcar-gen4-dmac"; reg = <0 0xe7350000 0 0x1000>, <0 0xe7300000 0 0x10000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 709>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7351000 { compatible = "renesas,dmac-r8a779f0", "renesas,rcar-gen4-dmac"; reg = <0 0xe7351000 0 0x1000>, <0 0xe7310000 0 0x10000>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 710>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; }; mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a779f0", "renesas,rcar-gen4-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; clock-names = "core", "clkh"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; status = "disabled"; }; ipmmu_rt0: iommu@ee480000 { compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee480000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 10>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_rt1: iommu@ee4c0000 { compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee4c0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 19>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_ds0: iommu@eed00000 { compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_hc: iommu@eed40000 { compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed40000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_mm: iommu@eefc0000 { compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeefc0000 0 0x20000>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; }; thermal-zones { sensor_thermal1: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; trips { sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; sensor_thermal2: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; trips { sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; sensor_thermal3: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; trips { sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; ufs30_clk: ufs30-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; }; |