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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 | /* * include/asm-xtensa/cacheasm.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2006 Tensilica Inc. */ #include <asm/cache.h> #include <asm/asmmacro.h> #include <linux/stringify.h> /* * Define cache functions as macros here so that they can be used * by the kernel and boot loader. We should consider moving them to a * library that can be linked by both. * * Locking * * ___unlock_dcache_all * ___unlock_icache_all * * Flush and invaldating * * ___flush_invalidate_dcache_{all|range|page} * ___flush_dcache_{all|range|page} * ___invalidate_dcache_{all|range|page} * ___invalidate_icache_{all|range|page} * */ .macro __loop_cache_unroll ar at insn size line_width max_immed .if (1 << (\line_width)) > (\max_immed) .set _reps, 1 .elseif (2 << (\line_width)) > (\max_immed) .set _reps, 2 .else .set _reps, 4 .endif __loopi \ar, \at, \size, (_reps << (\line_width)) .set _index, 0 .rep _reps \insn \ar, _index << (\line_width) .set _index, _index + 1 .endr __endla \ar, \at, _reps << (\line_width) .endm .macro __loop_cache_all ar at insn size line_width max_immed movi \ar, 0 __loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed .endm .macro __loop_cache_range ar as at insn line_width extui \at, \ar, 0, \line_width add \as, \as, \at __loops \ar, \as, \at, \line_width \insn \ar, 0 __endla \ar, \at, (1 << (\line_width)) .endm .macro __loop_cache_page ar at insn line_width max_immed __loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed .endm .macro ___unlock_dcache_all ar at #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 240 #endif .endm .macro ___unlock_icache_all ar at #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \ XCHAL_ICACHE_LINEWIDTH 240 #endif .endm .macro ___flush_invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 240 #endif .endm .macro ___flush_dcache_all ar at #if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 240 #endif .endm .macro ___invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___invalidate_icache_all ar at #if XCHAL_ICACHE_SIZE __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \ XCHAL_ICACHE_LINEWIDTH 1020 #endif .endm .macro ___flush_invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH #endif .endm .macro ___flush_dcache_range ar as at #if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH #endif .endm .macro ___invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH #endif .endm .macro ___invalidate_icache_range ar as at #if XCHAL_ICACHE_SIZE __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH #endif .endm .macro ___flush_invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___flush_dcache_page ar as #if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___invalidate_icache_page ar as #if XCHAL_ICACHE_SIZE __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020 #endif .endm |