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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 | // SPDX-License-Identifier: GPL-2.0-only /* * PCI interface driver for DW SPI Core * * Copyright (c) 2009, 2014 Intel Corporation. */ #include <linux/pci.h> #include <linux/pm_runtime.h> #include <linux/slab.h> #include <linux/spi/spi.h> #include <linux/module.h> #include "spi-dw.h" #define DRIVER_NAME "dw_spi_pci" /* HW info for MRST Clk Control Unit, 32b reg per controller */ #define MRST_SPI_CLK_BASE 100000000 /* 100m */ #define MRST_CLK_SPI_REG 0xff11d86c #define CLK_SPI_BDIV_OFFSET 0 #define CLK_SPI_BDIV_MASK 0x00000007 #define CLK_SPI_CDIV_OFFSET 9 #define CLK_SPI_CDIV_MASK 0x00000e00 #define CLK_SPI_DISABLE_OFFSET 8 struct dw_spi_pci_desc { int (*setup)(struct dw_spi *); u16 num_cs; u16 bus_num; u32 max_freq; }; static int dw_spi_pci_mid_init(struct dw_spi *dws) { void __iomem *clk_reg; u32 clk_cdiv; clk_reg = ioremap(MRST_CLK_SPI_REG, 16); if (!clk_reg) return -ENOMEM; /* Get SPI controller operating freq info */ clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32)); clk_cdiv &= CLK_SPI_CDIV_MASK; clk_cdiv >>= CLK_SPI_CDIV_OFFSET; dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1); iounmap(clk_reg); dw_spi_dma_setup_mfld(dws); return 0; } static int dw_spi_pci_generic_init(struct dw_spi *dws) { dw_spi_dma_setup_generic(dws); return 0; } static struct dw_spi_pci_desc dw_spi_pci_mid_desc_1 = { .setup = dw_spi_pci_mid_init, .num_cs = 5, .bus_num = 0, }; static struct dw_spi_pci_desc dw_spi_pci_mid_desc_2 = { .setup = dw_spi_pci_mid_init, .num_cs = 2, .bus_num = 1, }; static struct dw_spi_pci_desc dw_spi_pci_ehl_desc = { .setup = dw_spi_pci_generic_init, .num_cs = 2, .bus_num = -1, .max_freq = 100000000, }; static int dw_spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct dw_spi_pci_desc *desc = (struct dw_spi_pci_desc *)ent->driver_data; struct dw_spi *dws; int pci_bar = 0; int ret; ret = pcim_enable_device(pdev); if (ret) return ret; dws = devm_kzalloc(&pdev->dev, sizeof(*dws), GFP_KERNEL); if (!dws) return -ENOMEM; /* Get basic io resource and map it */ dws->paddr = pci_resource_start(pdev, pci_bar); pci_set_master(pdev); ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev)); if (ret) return ret; ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); if (ret < 0) return ret; dws->regs = pcim_iomap_table(pdev)[pci_bar]; dws->irq = pci_irq_vector(pdev, 0); /* * Specific handling for platforms, like dma setup, * clock rate, FIFO depth. */ if (desc) { dws->num_cs = desc->num_cs; dws->bus_num = desc->bus_num; dws->max_freq = desc->max_freq; if (desc->setup) { ret = desc->setup(dws); if (ret) goto err_free_irq_vectors; } } else { ret = -ENODEV; goto err_free_irq_vectors; } ret = dw_spi_add_host(&pdev->dev, dws); if (ret) goto err_free_irq_vectors; /* PCI hook and SPI hook use the same drv data */ pci_set_drvdata(pdev, dws); dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n", pdev->vendor, pdev->device); pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); pm_runtime_allow(&pdev->dev); return 0; err_free_irq_vectors: pci_free_irq_vectors(pdev); return ret; } static void dw_spi_pci_remove(struct pci_dev *pdev) { struct dw_spi *dws = pci_get_drvdata(pdev); pm_runtime_forbid(&pdev->dev); pm_runtime_get_noresume(&pdev->dev); dw_spi_remove_host(dws); pci_free_irq_vectors(pdev); } #ifdef CONFIG_PM_SLEEP static int dw_spi_pci_suspend(struct device *dev) { struct dw_spi *dws = dev_get_drvdata(dev); return dw_spi_suspend_host(dws); } static int dw_spi_pci_resume(struct device *dev) { struct dw_spi *dws = dev_get_drvdata(dev); return dw_spi_resume_host(dws); } #endif static SIMPLE_DEV_PM_OPS(dw_spi_pci_pm_ops, dw_spi_pci_suspend, dw_spi_pci_resume); static const struct pci_device_id dw_spi_pci_ids[] = { /* Intel MID platform SPI controller 0 */ /* * The access to the device 8086:0801 is disabled by HW, since it's * exclusively used by SCU to communicate with MSIC. */ /* Intel MID platform SPI controller 1 */ { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&dw_spi_pci_mid_desc_1}, /* Intel MID platform SPI controller 2 */ { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&dw_spi_pci_mid_desc_2}, /* Intel Elkhart Lake PSE SPI controllers */ { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, {}, }; MODULE_DEVICE_TABLE(pci, dw_spi_pci_ids); static struct pci_driver dw_spi_pci_driver = { .name = DRIVER_NAME, .id_table = dw_spi_pci_ids, .probe = dw_spi_pci_probe, .remove = dw_spi_pci_remove, .driver = { .pm = &dw_spi_pci_pm_ops, }, }; module_pci_driver(dw_spi_pci_driver); MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); MODULE_DESCRIPTION("PCI interface driver for DW SPI Core"); MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS(SPI_DW_CORE); |