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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Code to handle x86 style IRQs plus some generic interrupt stuff. * * Copyright (C) 1992 Linus Torvalds * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) * Copyright (C) 1999-2000 Grant Grundler * Copyright (c) 2005 Matthew Wilcox */ #include <linux/bitops.h> #include <linux/errno.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/kernel_stat.h> #include <linux/seq_file.h> #include <linux/types.h> #include <linux/sched/task_stack.h> #include <asm/io.h> #include <asm/softirq_stack.h> #include <asm/smp.h> #include <asm/ldcw.h> #undef PARISC_IRQ_CR16_COUNTS extern irqreturn_t timer_interrupt(int, void *); extern irqreturn_t ipi_interrupt(int, void *); #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq)) /* Bits in EIEM correlate with cpu_irq_action[]. ** Numbered *Big Endian*! (ie bit 0 is MSB) */ static volatile unsigned long cpu_eiem = 0; /* ** local ACK bitmap ... habitually set to 1, but reset to zero ** between ->ack() and ->end() of the interrupt to prevent ** re-interruption of a processing interrupt. */ static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; static void cpu_mask_irq(struct irq_data *d) { unsigned long eirr_bit = EIEM_MASK(d->irq); cpu_eiem &= ~eirr_bit; /* Do nothing on the other CPUs. If they get this interrupt, * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't * handle it, and the set_eiem() at the bottom will ensure it * then gets disabled */ } static void __cpu_unmask_irq(unsigned int irq) { unsigned long eirr_bit = EIEM_MASK(irq); cpu_eiem |= eirr_bit; /* This is just a simple NOP IPI. But what it does is cause * all the other CPUs to do a set_eiem(cpu_eiem) at the end * of the interrupt handler */ smp_send_all_nop(); } static void cpu_unmask_irq(struct irq_data *d) { __cpu_unmask_irq(d->irq); } void cpu_ack_irq(struct irq_data *d) { unsigned long mask = EIEM_MASK(d->irq); int cpu = smp_processor_id(); /* Clear in EIEM so we can no longer process */ per_cpu(local_ack_eiem, cpu) &= ~mask; /* disable the interrupt */ set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); /* and now ack it */ mtctl(mask, 23); } void cpu_eoi_irq(struct irq_data *d) { unsigned long mask = EIEM_MASK(d->irq); int cpu = smp_processor_id(); /* set it in the eiems---it's no longer in process */ per_cpu(local_ack_eiem, cpu) |= mask; /* enable the interrupt */ set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); } #ifdef CONFIG_SMP int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest) { int cpu_dest; /* timer and ipi have to always be received on all CPUs */ if (irqd_is_per_cpu(d)) return -EINVAL; cpu_dest = cpumask_first_and(dest, cpu_online_mask); if (cpu_dest >= nr_cpu_ids) cpu_dest = cpumask_first(cpu_online_mask); return cpu_dest; } #endif static struct irq_chip cpu_interrupt_type = { .name = "CPU", .irq_mask = cpu_mask_irq, .irq_unmask = cpu_unmask_irq, .irq_ack = cpu_ack_irq, .irq_eoi = cpu_eoi_irq, /* XXX: Needs to be written. We managed without it so far, but * we really ought to write it. */ .irq_retrigger = NULL, }; DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); #define irq_stats(x) (&per_cpu(irq_stat, x)) /* * /proc/interrupts printing for arch specific interrupts */ int arch_show_interrupts(struct seq_file *p, int prec) { int j; #ifdef CONFIG_DEBUG_STACKOVERFLOW seq_printf(p, "%*s: ", prec, "STK"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->kernel_stack_usage); seq_puts(p, " Kernel stack usage\n"); # ifdef CONFIG_IRQSTACKS seq_printf(p, "%*s: ", prec, "IST"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_stack_usage); seq_puts(p, " Interrupt stack usage\n"); # endif #endif #ifdef CONFIG_SMP if (num_online_cpus() > 1) { seq_printf(p, "%*s: ", prec, "RES"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); seq_puts(p, " Rescheduling interrupts\n"); seq_printf(p, "%*s: ", prec, "CAL"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_call_count); seq_puts(p, " Function call interrupts\n"); } #endif seq_printf(p, "%*s: ", prec, "UAH"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_unaligned_count); seq_puts(p, " Unaligned access handler traps\n"); seq_printf(p, "%*s: ", prec, "FPA"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_fpassist_count); seq_puts(p, " Floating point assist traps\n"); seq_printf(p, "%*s: ", prec, "TLB"); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); seq_puts(p, " TLB shootdowns\n"); return 0; } int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j; unsigned long flags; if (i == 0) { seq_puts(p, " "); for_each_online_cpu(j) seq_printf(p, " CPU%d", j); #ifdef PARISC_IRQ_CR16_COUNTS seq_printf(p, " [min/avg/max] (CPU cycle counts)"); #endif seq_putc(p, '\n'); } if (i < NR_IRQS) { struct irq_desc *desc = irq_to_desc(i); struct irqaction *action; raw_spin_lock_irqsave(&desc->lock, flags); action = desc->action; if (!action) goto skip; seq_printf(p, "%3d: ", i); for_each_online_cpu(j) seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, j)); seq_printf(p, " %14s", irq_desc_get_chip(desc)->name); #ifndef PARISC_IRQ_CR16_COUNTS seq_printf(p, " %s", action->name); while ((action = action->next)) seq_printf(p, ", %s", action->name); #else for ( ;action; action = action->next) { unsigned int k, avg, min, max; min = max = action->cr16_hist[0]; for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { int hist = action->cr16_hist[k]; if (hist) { avg += hist; } else break; if (hist > max) max = hist; if (hist < min) min = hist; } avg /= k; seq_printf(p, " %s[%d/%d/%d]", action->name, min,avg,max); } #endif seq_putc(p, '\n'); skip: raw_spin_unlock_irqrestore(&desc->lock, flags); } if (i == NR_IRQS) arch_show_interrupts(p, 3); return 0; } /* ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data. ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit. ** ** To use txn_XXX() interfaces, get a Virtual IRQ first. ** Then use that to get the Transaction address and data. */ int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) { if (irq_has_action(irq)) return -EBUSY; if (irq_get_chip(irq) != &cpu_interrupt_type) return -EBUSY; /* for iosapic interrupts */ if (type) { irq_set_chip_and_handler(irq, type, handle_percpu_irq); irq_set_chip_data(irq, data); __cpu_unmask_irq(irq); } return 0; } int txn_claim_irq(int irq) { return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq; } /* * The bits_wide parameter accommodates the limitations of the HW/SW which * use these bits: * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) * V-class (EPIC): 6 bits * N/L/A-class (iosapic): 8 bits * PCI 2.2 MSI: 16 bits * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric) * * On the service provider side: * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register) * o PA 2.0 wide mode 6-bits (per processor) * o IA64 8-bits (0-256 total) * * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported * by the processor...and the N/L-class I/O subsystem supports more bits than * PA2.0 has. The first case is the problem. */ int txn_alloc_irq(unsigned int bits_wide) { int irq; /* never return irq 0 cause that's the interval timer */ for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) { if (cpu_claim_irq(irq, NULL, NULL) < 0) continue; if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide)) continue; return irq; } /* unlikely, but be prepared */ return -1; } unsigned long txn_affinity_addr(unsigned int irq, int cpu) { #ifdef CONFIG_SMP struct irq_data *d = irq_get_irq_data(irq); irq_data_update_affinity(d, cpumask_of(cpu)); #endif return per_cpu(cpu_data, cpu).txn_addr; } unsigned long txn_alloc_addr(unsigned int virt_irq) { static int next_cpu = -1; next_cpu++; /* assign to "next" CPU we want this bugger on */ /* validate entry */ while ((next_cpu < nr_cpu_ids) && (!per_cpu(cpu_data, next_cpu).txn_addr || !cpu_online(next_cpu))) next_cpu++; if (next_cpu >= nr_cpu_ids) next_cpu = 0; /* nothing else, assign monarch */ return txn_affinity_addr(virt_irq, next_cpu); } unsigned int txn_alloc_data(unsigned int virt_irq) { return virt_irq - CPU_IRQ_BASE; } static inline int eirr_to_irq(unsigned long eirr) { int bit = fls_long(eirr); return (BITS_PER_LONG - bit) + TIMER_IRQ; } #ifdef CONFIG_IRQSTACKS /* * IRQ STACK - used for irq handler */ #ifdef CONFIG_64BIT #define IRQ_STACK_SIZE (4096 << 4) /* 64k irq stack size */ #else #define IRQ_STACK_SIZE (4096 << 3) /* 32k irq stack size */ #endif union irq_stack_union { unsigned long stack[IRQ_STACK_SIZE/sizeof(unsigned long)]; volatile unsigned int slock[4]; volatile unsigned int lock[1]; }; static DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = { .slock = { 1,1,1,1 }, }; #endif int sysctl_panic_on_stackoverflow = 1; static inline void stack_overflow_check(struct pt_regs *regs) { #ifdef CONFIG_DEBUG_STACKOVERFLOW #define STACK_MARGIN (256*6) unsigned long stack_start = (unsigned long) task_stack_page(current); unsigned long sp = regs->gr[30]; unsigned long stack_usage; unsigned int *last_usage; int cpu = smp_processor_id(); /* if sr7 != 0, we interrupted a userspace process which we do not want * to check for stack overflow. We will only check the kernel stack. */ if (regs->sr[7]) return; /* exit if already in panic */ if (sysctl_panic_on_stackoverflow < 0) return; /* calculate kernel stack usage */ stack_usage = sp - stack_start; #ifdef CONFIG_IRQSTACKS if (likely(stack_usage <= THREAD_SIZE)) goto check_kernel_stack; /* found kernel stack */ /* check irq stack usage */ stack_start = (unsigned long) &per_cpu(irq_stack_union, cpu).stack; stack_usage = sp - stack_start; last_usage = &per_cpu(irq_stat.irq_stack_usage, cpu); if (unlikely(stack_usage > *last_usage)) *last_usage = stack_usage; if (likely(stack_usage < (IRQ_STACK_SIZE - STACK_MARGIN))) return; pr_emerg("stackcheck: %s will most likely overflow irq stack " "(sp:%lx, stk bottom-top:%lx-%lx)\n", current->comm, sp, stack_start, stack_start + IRQ_STACK_SIZE); goto panic_check; check_kernel_stack: #endif /* check kernel stack usage */ last_usage = &per_cpu(irq_stat.kernel_stack_usage, cpu); if (unlikely(stack_usage > *last_usage)) *last_usage = stack_usage; if (likely(stack_usage < (THREAD_SIZE - STACK_MARGIN))) return; pr_emerg("stackcheck: %s will most likely overflow kernel stack " "(sp:%lx, stk bottom-top:%lx-%lx)\n", current->comm, sp, stack_start, stack_start + THREAD_SIZE); #ifdef CONFIG_IRQSTACKS panic_check: #endif if (sysctl_panic_on_stackoverflow) { sysctl_panic_on_stackoverflow = -1; /* disable further checks */ panic("low stack detected by irq handler - check messages\n"); } #endif } #ifdef CONFIG_IRQSTACKS /* in entry.S: */ void call_on_stack(unsigned long p1, void *func, unsigned long new_stack); static void execute_on_irq_stack(void *func, unsigned long param1) { union irq_stack_union *union_ptr; unsigned long irq_stack; volatile unsigned int *irq_stack_in_use; union_ptr = &per_cpu(irq_stack_union, smp_processor_id()); irq_stack = (unsigned long) &union_ptr->stack; irq_stack = ALIGN(irq_stack + sizeof(irq_stack_union.slock), FRAME_ALIGN); /* align for stack frame usage */ /* We may be called recursive. If we are already using the irq stack, * just continue to use it. Use spinlocks to serialize * the irq stack usage. */ irq_stack_in_use = (volatile unsigned int *)__ldcw_align(union_ptr); if (!__ldcw(irq_stack_in_use)) { void (*direct_call)(unsigned long p1) = func; /* We are using the IRQ stack already. * Do direct call on current stack. */ direct_call(param1); return; } /* This is where we switch to the IRQ stack. */ call_on_stack(param1, func, irq_stack); /* free up irq stack usage. */ *irq_stack_in_use = 1; } #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK void do_softirq_own_stack(void) { execute_on_irq_stack(__do_softirq, 0); } #endif #endif /* CONFIG_IRQSTACKS */ /* ONLY called from entry.S:intr_extint() */ void do_cpu_irq_mask(struct pt_regs *regs) { struct pt_regs *old_regs; unsigned long eirr_val; int irq, cpu = smp_processor_id(); struct irq_data *irq_data; #ifdef CONFIG_SMP cpumask_t dest; #endif old_regs = set_irq_regs(regs); local_irq_disable(); irq_enter(); eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu); if (!eirr_val) goto set_out; irq = eirr_to_irq(eirr_val); irq_data = irq_get_irq_data(irq); /* Filter out spurious interrupts, mostly from serial port at bootup */ if (unlikely(!irq_desc_has_action(irq_data_to_desc(irq_data)))) goto set_out; #ifdef CONFIG_SMP cpumask_copy(&dest, irq_data_get_affinity_mask(irq_data)); if (irqd_is_per_cpu(irq_data) && !cpumask_test_cpu(smp_processor_id(), &dest)) { int cpu = cpumask_first(&dest); printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", irq, smp_processor_id(), cpu); gsc_writel(irq + CPU_IRQ_BASE, per_cpu(cpu_data, cpu).hpa); goto set_out; } #endif stack_overflow_check(regs); #ifdef CONFIG_IRQSTACKS execute_on_irq_stack(&generic_handle_irq, irq); #else generic_handle_irq(irq); #endif /* CONFIG_IRQSTACKS */ out: irq_exit(); set_irq_regs(old_regs); return; set_out: set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); goto out; } static void claim_cpu_irqs(void) { unsigned long flags = IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL; int i; for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { irq_set_chip_and_handler(i, &cpu_interrupt_type, handle_percpu_irq); } irq_set_handler(TIMER_IRQ, handle_percpu_irq); if (request_irq(TIMER_IRQ, timer_interrupt, flags, "timer", NULL)) pr_err("Failed to register timer interrupt\n"); #ifdef CONFIG_SMP irq_set_handler(IPI_IRQ, handle_percpu_irq); if (request_irq(IPI_IRQ, ipi_interrupt, IRQF_PERCPU, "IPI", NULL)) pr_err("Failed to register IPI interrupt\n"); #endif } void init_IRQ(void) { local_irq_disable(); /* PARANOID - should already be disabled */ mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ #ifdef CONFIG_SMP if (!cpu_eiem) { claim_cpu_irqs(); cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ); } #else claim_cpu_irqs(); cpu_eiem = EIEM_MASK(TIMER_IRQ); #endif set_eiem(cpu_eiem); /* EIEM : enable all external intr */ } |